mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-21 04:42:53 +08:00
1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
135 lines
1.8 KiB
ArmAsm
135 lines
1.8 KiB
ArmAsm
# mach: all
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# output:
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# sim: --environment operating
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# as: -W
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.include "t-macros.i"
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start
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;;; Try out each bit in the PSW
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loadpsw2 PSW_SM
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checkpsw2 1 PSW_SM
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loadpsw2 PSW_01
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checkpsw2 2 0 ;; PSW_01
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loadpsw2 PSW_EA
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checkpsw2 3 PSW_EA
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loadpsw2 PSW_DB
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checkpsw2 4 PSW_DB
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loadpsw2 PSW_DM
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checkpsw2 5 0 ;; PSW_DM
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loadpsw2 PSW_IE
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checkpsw2 6 PSW_IE
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loadpsw2 PSW_RP
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checkpsw2 7 PSW_RP
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loadpsw2 PSW_MD
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checkpsw2 8 PSW_MD
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loadpsw2 PSW_FX|PSW_ST
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checkpsw2 9 PSW_FX|PSW_ST
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;; loadpsw2 PSW_ST
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;; checkpsw2 10
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loadpsw2 PSW_10
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checkpsw2 11 0 ;; PSW_10
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loadpsw2 PSW_11
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checkpsw2 12 0 ;; PSW_11
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loadpsw2 PSW_F0
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checkpsw2 13 PSW_F0
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loadpsw2 PSW_F1
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checkpsw2 14 PSW_F1
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loadpsw2 PSW_14
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checkpsw2 15 0 ;; PSW_14
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loadpsw2 PSW_C
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checkpsw2 16 PSW_C
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;;; Check that bit 0 (LSB) of the MOD_E & MOD_S registers are stuck at ZERO.
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ldi r6, #0xdead
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mvtc r6, cr10
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ldi r6, #0xbeef
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mvtc r6, cr11
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mvfc r7, cr10
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check 17 r7 0xdeac
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mvfc r7, cr11
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check 18 r7 0xbeee
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;;; Check that certain bits of the PSW, DPSW and BPSW are hardwired to zero
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psw_ffff:
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ldi r6, 0xffff
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mvtc r6, psw
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mvfc r7, psw
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check 18 r7 0xb7cd
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bpsw_ffff:
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ldi r6, 0xffff
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mvtc r6, bpsw
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mvfc r7, bpsw
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check 18 r7 0xb7cd
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dpsw_ffff:
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ldi r6, 0xffff
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mvtc r6, dpsw
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mvfc r7, dpsw
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check 18 r7 0xb7cd
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;;; Another check. Very similar
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psw_dfff:
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ldi r6, 0xdfff
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mvtc r6, psw
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mvfc r7, psw
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check 18 r7 0x97cd
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bpsw_dfff:
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ldi r6, 0xdfff
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mvtc r6, bpsw
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mvfc r7, bpsw
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check 18 r7 0x97cd
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dpsw_dfff:
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ldi r6, 0xdfff
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mvtc r6, dpsw
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mvfc r7, dpsw
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check 18 r7 0x97cd
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;;; And again.
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psw_8005:
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ldi r6, 0x8005
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mvtc r6, psw
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mvfc r7, psw
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check 18 r7 0x8005
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bpsw_8005:
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ldi r6, 0x8005
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mvtc r6, bpsw
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mvfc r7, bpsw
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check 18 r7 0x8005
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dpsw_8005:
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ldi r6, 0x8005
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mvtc r6, dpsw
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mvfc r7, dpsw
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check 18 r7 0x8005
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exit0
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