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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
387 lines
7.3 KiB
ArmAsm
387 lines
7.3 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmrj_mvpop/c_seq_ex2_mmrj_mvpop.dsp
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// Spec Reference: sequencer stage ex2 ( mmr + jump + regmv + pushpopmultiple)
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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include(std.inc)
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include(selfcheck.inc)
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include(gen_int.inc)
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INIT_R_REGS(0);
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INIT_P_REGS(0);
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INIT_I_REGS(0); // initialize the dsp address regs
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INIT_M_REGS(0);
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INIT_L_REGS(0);
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INIT_B_REGS(0);
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//CHECK_INIT(p5, 0xe0000000);
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include(symtable.inc)
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CHECK_INIT_DEF(p5);
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#ifndef STACKSIZE
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#define STACKSIZE 0x10
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#endif
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#ifndef EVT
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#define EVT 0xFFE02000
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#endif
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#ifndef EVT15
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#define EVT15 0xFFE0203C
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#endif
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#ifndef EVT_OVERRIDE
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#define EVT_OVERRIDE 0xFFE02100
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#endif
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#ifndef ITABLE
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#define ITABLE DATA_ADDR_1
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#endif
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GEN_INT_INIT(ITABLE) // set location for interrupt table
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//
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// Reset/Bootstrap Code
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// (Here we should set the processor operating modes, initialize registers,
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//
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BOOT:
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// in reset mode now
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LD32_LABEL(sp, KSTACK); // setup the stack pointer
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FP = SP; // and frame pointer
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LD32(p0, EVT); // Setup Event Vectors and Handlers
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LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
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[ P0 ++ ] = R0;
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[ P0 ++ ] = R0; // IVT4 not used
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LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
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[ P0 ++ ] = R0;
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LD32(p0, EVT_OVERRIDE);
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R0 = 0;
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[ P0 ++ ] = R0;
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R0 = -1; // Change this to mask interrupts (*)
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[ P0 ] = R0; // IMASK
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CSYNC;
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DUMMY:
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R0 = 0 (Z);
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LT0 = r0; // set loop counters to something deterministic
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LB0 = r0;
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LC0 = r0;
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LT1 = r0;
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LB1 = r0;
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LC1 = r0;
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ASTAT = r0; // reset other internal regs
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// The following code sets up the test for running in USER mode
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LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
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// ReturnFromInterrupt (RTI)
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RETI = r0; // We need to load the return address
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// Comment the following line for a USER Mode test
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JUMP STARTSUP; // jump to code start for SUPERVISOR mode
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RTI;
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STARTSUP:
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LD32_LABEL(p1, BEGIN);
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LD32(p0, EVT15);
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[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
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RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
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// SUPERVISOR MODE & go to different RAISE in supervisor mode
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// until the end of the test.
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NOP; // Workaround for Bug 217
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RTI;
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//
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// The Main Program
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//
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STARTUSER:
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LD32_LABEL(sp, USTACK); // setup the stack pointer
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FP = SP; // set frame pointer
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JUMP BEGIN;
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//*********************************************************************
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BEGIN:
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// COMMENT the following line for USER MODE tests
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[ -- SP ] = RETI; // enable interrupts in supervisor mode
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// **** YOUR CODE GOES HERE ****
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// PUT YOUR TEST HERE!
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// PUSH
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LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
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LD32(p2, DATA_ADDR_1);
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LD32(p3, 0xab5fd490);
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LD32(p4, 0xa581bd94);
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LD32(r2, 0x14789232);
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[ P1 ] = R2;
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CSYNC;
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R0 = 0x01;
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R1 = 0x02;
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R2 = 0x03;
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R3 = 0x04;
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R4 = 0x05;
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R5 = 0x06;
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R6 = 0x07;
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R7 = 0x08;
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[ -- SP ] = ( R7:0 );
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// RAISE 2; // RTN
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[ P1 ] = R0;
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JUMP.S LABEL1;
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P1 = R1;
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R2 = P1;
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[ -- SP ] = ( R7:0 );
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R1 = 0x12;
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R2 = 0x13;
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R3 = 0x14;
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R4 = 0x15;
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R5 = 0x16;
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R6 = 0x17;
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R7 = 0x18;
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LABEL1:
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// RAISE 5; // RTI
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P2 = R2;
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R3 = P2;
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[ -- SP ] = ( R7:0 );
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R2 = 0x23;
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R3 = 0x24;
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R4 = 0x25;
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R5 = 0x26;
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R6 = 0x27;
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R7 = 0x28;
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// wrt-rd EVT5 = 0xFFE02034
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LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
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// RAISE 6; // RTI
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R0 = [ P1 ];
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JUMP.S LABEL2;
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P3 = R3;
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R4 = P3;
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[ -- SP ] = ( R7:0 );
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// POP
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R0 = 0x00;
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R1 = 0x00;
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R2 = 0x00;
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R3 = 0x00;
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R4 = 0x00;
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R5 = 0x00;
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R6 = 0x00;
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R7 = 0x00;
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LABEL2:
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CHECKREG(r0, 0x00000001);
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// RAISE 7; // RTI
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P4 = R4;
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R5 = P4;
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( R7:0 ) = [ SP ++ ];
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CHECKREG(r0, 0x00000001);
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CHECKREG(r1, 0x00000002);
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CHECKREG(r2, 0x00000003);
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CHECKREG(r3, 0x00000003);
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CHECKREG(r4, 0x00000005);
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CHECKREG(r5, 0x00000006);
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CHECKREG(r6, 0x00000007);
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CHECKREG(r7, 0x00000008);
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// wrt-rd EVT13 = 0xFFE02034
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LD32(p1, 0xFFE02034);
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// RAISE 8; // RTI
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R0 = [ P1 ];
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JUMP.S LABEL3;
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P1 = R5;
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R6 = P1;
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( R7:0 ) = [ SP ++ ];
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//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
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//CHECKREG(r1, 0x000000b2); // so they cannot appear here
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//CHECKREG(r2, 0x000000c3);
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//CHECKREG(r3, 0x000000d4);
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//CHECKREG(r4, 0x000000e5);
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//CHECKREG(r5, 0x000000f6);
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//CHECKREG(r6, 0x00000017);
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//CHECKREG(r7, 0x00000028);
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R0 = 12;
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R1 = 13;
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R2 = 14;
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R3 = 15;
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R4 = 16;
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R5 = 17;
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R6 = 18;
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R7 = 19;
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LABEL3:
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CHECKREG(r0, 0x00000001);
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// RAISE 9; // RTI
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P2 = R6;
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R7 = P2;
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( R7:0 ) = [ SP ++ ];
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CHECKREG(r0, 0x00000001);
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CHECKREG(r1, 0x00000002);
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CHECKREG(r2, 0x00000003);
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CHECKREG(r3, 0x00000004);
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CHECKREG(r4, 0x00000005);
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CHECKREG(r5, 0x00000006);
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CHECKREG(r6, 0x00000007);
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CHECKREG(r7, 0x00000008);
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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CHECKREG(r0, 0x00000000);
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CHECKREG(r1, 0x00000000);
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CHECKREG(r2, 0x00000000);
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CHECKREG(r3, 0x00000000);
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END:
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dbg_pass; // End the test
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//*********************************************************************
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//
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// Handlers for Events
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//
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EHANDLE: // Emulation Handler 0
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RTE;
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RHANDLE: // Reset Handler 1
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RTI;
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NHANDLE: // NMI Handler 2
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I0 += 2;
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RTN;
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XHANDLE: // Exception Handler 3
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R1 = 3;
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RTX;
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HWHANDLE: // HW Error Handler 5
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I1 += 2;
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RTI;
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THANDLE: // Timer Handler 6
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I2 += 2;
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RTI;
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I7HANDLE: // IVG 7 Handler
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I3 += 2;
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RTI;
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I8HANDLE: // IVG 8 Handler
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I0 += 2;
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RTI;
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I9HANDLE: // IVG 9 Handler
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I0 += 2;
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RTI;
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I10HANDLE: // IVG 10 Handler
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R7 = 10;
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RTI;
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I11HANDLE: // IVG 11 Handler
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I0 = R0;
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I1 = R1;
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I2 = R2;
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I3 = R3;
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M0 = R4;
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R0 = 11;
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RTI;
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I12HANDLE: // IVG 12 Handler
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R1 = 12;
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RTI;
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I13HANDLE: // IVG 13 Handler
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R2 = 13;
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RTI;
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I14HANDLE: // IVG 14 Handler
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R3 = 14;
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RTI;
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I15HANDLE: // IVG 15 Handler
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R4 = 15;
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RTI;
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NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
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//
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// Data Segment
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//
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.data
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DATA:
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.space (0x10);
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// Stack Segments (Both Kernel and User)
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.space (STACKSIZE);
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KSTACK:
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.space (STACKSIZE);
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USTACK:
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