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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
174 lines
3.0 KiB
ArmAsm
174 lines
3.0 KiB
ArmAsm
//Original:/testcases/core/c_pushpopmultiple_dreg/c_pushpopmultiple_dreg.dsp
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// Spec Reference: pushpopmultiple dreg
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# mach: bfin
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.include "testutils.inc"
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start
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FP = SP;
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imm32 r0, 0x00000000;
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ASTAT = r0;
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R0 = 0x01;
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R1 = 0x02;
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R2 = 0x03;
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R3 = 0x04;
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R4 = 0x05;
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R5 = 0x06;
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R6 = 0x07;
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R7 = 0x08;
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[ -- SP ] = ( R7:0 );
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R0 = 0;
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R1 = 0;
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R2 = 0;
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R3 = 0;
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R4 = 0;
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R5 = 0;
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R6 = 0;
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R7 = 0;
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( R7:0 ) = [ SP ++ ];
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00000002;
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CHECKREG r2, 0x00000003;
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CHECKREG r3, 0x00000004;
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CHECKREG r4, 0x00000005;
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CHECKREG r5, 0x00000006;
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CHECKREG r6, 0x00000007;
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CHECKREG r7, 0x00000008;
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R1 = 0x12;
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R2 = 0x13;
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R3 = 0x14;
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R4 = 0x15;
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R5 = 0x16;
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R6 = 0x17;
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R7 = 0x18;
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[ -- SP ] = ( R7:1 );
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R1 = 0;
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R2 = 0;
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R3 = 0;
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R4 = 0;
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R5 = 0;
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R6 = 0;
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R7 = 0;
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( R7:1 ) = [ SP ++ ];
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00000012;
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CHECKREG r2, 0x00000013;
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CHECKREG r3, 0x00000014;
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CHECKREG r4, 0x00000015;
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CHECKREG r5, 0x00000016;
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CHECKREG r6, 0x00000017;
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CHECKREG r7, 0x00000018;
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R2 = 0x23;
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R3 = 0x24;
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R4 = 0x25;
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R5 = 0x26;
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R6 = 0x27;
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R7 = 0x28;
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[ -- SP ] = ( R7:2 );
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R2 = 0;
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R3 = 0;
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R4 = 0;
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R5 = 0;
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R6 = 0;
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R7 = 0;
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( R7:2 ) = [ SP ++ ];
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00000012;
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CHECKREG r2, 0x00000023;
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CHECKREG r3, 0x00000024;
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CHECKREG r4, 0x00000025;
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CHECKREG r5, 0x00000026;
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CHECKREG r6, 0x00000027;
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CHECKREG r7, 0x00000028;
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R3 = 0x34;
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R4 = 0x35;
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R5 = 0x36;
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R6 = 0x37;
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R7 = 0x38;
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[ -- SP ] = ( R7:3 );
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R3 = 0;
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R4 = 0;
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R5 = 0;
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R6 = 0;
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R7 = 0;
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( R7:3 ) = [ SP ++ ];
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00000012;
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CHECKREG r2, 0x00000023;
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CHECKREG r3, 0x00000034;
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CHECKREG r4, 0x00000035;
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CHECKREG r5, 0x00000036;
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CHECKREG r6, 0x00000037;
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CHECKREG r7, 0x00000038;
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R4 = 0x45 (X);
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R5 = 0x46 (X);
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R6 = 0x47 (X);
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R7 = 0x48 (X);
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[ -- SP ] = ( R7:4 );
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R4 = 0;
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R5 = 0;
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R6 = 0;
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R7 = 0;
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( R7:4 ) = [ SP ++ ];
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00000012;
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CHECKREG r2, 0x00000023;
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CHECKREG r3, 0x00000034;
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CHECKREG r4, 0x00000045;
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CHECKREG r5, 0x00000046;
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CHECKREG r6, 0x00000047;
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CHECKREG r7, 0x00000048;
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R5 = 0x56 (X);
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R6 = 0x57 (X);
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R7 = 0x58 (X);
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[ -- SP ] = ( R7:5 );
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R5 = 0;
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R6 = 0;
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R7 = 0;
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( R7:5 ) = [ SP ++ ];
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00000012;
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CHECKREG r2, 0x00000023;
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CHECKREG r3, 0x00000034;
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CHECKREG r4, 0x00000045;
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CHECKREG r5, 0x00000056;
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CHECKREG r6, 0x00000057;
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CHECKREG r7, 0x00000058;
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R6 = 0x67 (X);
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R7 = 0x68 (X);
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[ -- SP ] = ( R7:6 );
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R6 = 0;
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R7 = 0;
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( R7:6 ) = [ SP ++ ];
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00000012;
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CHECKREG r2, 0x00000023;
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CHECKREG r3, 0x00000034;
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CHECKREG r4, 0x00000045;
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CHECKREG r5, 0x00000056;
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CHECKREG r6, 0x00000067;
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CHECKREG r7, 0x00000068;
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R7 = 0x78 (X);
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[ -- SP ] = ( R7:7 );
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R7 = 0;
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( R7:7 ) = [ SP ++ ];
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00000012;
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CHECKREG r2, 0x00000023;
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CHECKREG r3, 0x00000034;
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CHECKREG r4, 0x00000045;
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CHECKREG r5, 0x00000056;
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CHECKREG r6, 0x00000067;
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CHECKREG r7, 0x00000078;
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pass
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