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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
399 lines
7.6 KiB
ArmAsm
399 lines
7.6 KiB
ArmAsm
# Blackfin testcase for the CEC
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# mach: bfin
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# sim: --environment operating
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.include "testutils.inc"
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start
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INIT_R_REGS 0;
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INIT_P_REGS 0;
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INIT_I_REGS 0;
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INIT_M_REGS 0;
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INIT_L_REGS 0;
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INIT_B_REGS 0;
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CLI R1; // inhibit events during MMR writes
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loadsym sp, USTACK; // setup the user stack pointer
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usp = sp; // and frame pointer
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loadsym sp, KSTACK; // setup the stack pointer
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fp = sp; // and frame pointer
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imm32 p0, 0xFFE02000;
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loadsym r0, EHANDLE; // Emulation Handler (Int0)
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[p0++] = r0;
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loadsym r0, RHANDLE; // Reset Handler (Int1)
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[p0++] = r0;
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loadsym r0, NHANDLE; // NMI Handler (Int2)
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[p0++] = r0;
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loadsym r0, XHANDLE; // Exception Handler (Int3)
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[p0++] = r0;
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[p0++] = r0; // EVT4 not used global Interr Enable (INT4)
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loadsym r0, HWHANDLE; // HW Error Handler (Int5)
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[p0++] = r0;
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loadsym r0, THANDLE; // Timer Handler (Int6)
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[p0++] = r0;
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loadsym r0, I7HANDLE; // IVG7 Handler
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[p0++] = r0;
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loadsym r0, I8HANDLE; // IVG8 Handler
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[p0++] = r0;
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loadsym r0, I9HANDLE; // IVG9 Handler
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[p0++] = r0;
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loadsym r0, I10HANDLE;// IVG10 Handler
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[p0++] = r0;
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loadsym r0, I11HANDLE;// IVG11 Handler
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[p0++] = r0;
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loadsym r0, I12HANDLE;// IVG12 Handler
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[p0++] = r0;
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loadsym r0, I13HANDLE;// IVG13 Handler
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[p0++] = r0;
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loadsym r0, I14HANDLE;// IVG14 Handler
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[p0++] = r0;
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loadsym r0, I15HANDLE;// IVG15 Handler
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[p0++] = r0;
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imm32 p0, 0xFFE02100 // EVT_OVERRIDE
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r0 = 0;
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[p0++] = r0;
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r1 = -1; // Change this to mask interrupts (*)
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csync; // wait for MMR writes to finish
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sti r1; // sync and reenable events (implicit write to IMASK)
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imm32 p0, 0xFFE02104;
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r0 = [p0];
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// ckeck that sti allows the lower 5 bits of imask to be written
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CHECKREG r0, 0xffff;
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DUMMY:
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r0 = 0 (z);
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LT0 = r0; // set loop counters to something deterministic
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LB0 = r0;
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LC0 = r0;
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LT1 = r0;
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LB1 = r0;
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LC1 = r0;
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ASTAT = r0; // reset other internal regs
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SYSCFG = r0;
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RETS = r0; // prevent X's breaking LINK instruction
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// The following code sets up the test for running in USER mode
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loadsym r0, STARTUSER;// One gets to user mode by doing a
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// ReturnFromInterrupt (RTI)
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RETI = r0; // We need to load the return address
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// Comment the following line for a USER Mode test
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JUMP STARTSUP; // jump to code start for SUPERVISOR mode
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RTI;
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STARTSUP:
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loadsym p1, BEGIN;
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imm32 p0, (0xFFE02000 + 4 * 15);
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CLI R1; // inhibit events during write to MMR
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[p0] = p1; // IVG15 (General) handler (Int 15) load with start
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csync; // wait for it
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sti r1; // reenable events with proper imask
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RAISE 15; // after we RTI, INT 15 should be taken
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RTI;
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//
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// The Main Program
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//
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STARTUSER:
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LINK 0; // change for how much stack frame space you need.
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JUMP BEGIN;
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// *********************************************************************
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BEGIN:
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// COMMENT the following line for USER MODE tests
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[--sp] = RETI; // enable interrupts in supervisor mode
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// **** YOUR CODE GOES HERE ****
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// EVTx
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// wrt-rd EVT0: 0 bits, rw=0 = 0xFFE02000
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imm32 p0, 0xFFE02000;
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imm32 r0, 0x00000000
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[p0] = r0;
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// wrt-rd EVT1: 32 bits, rw=0 = 0xFFE02004
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imm32 p0, 0xFFE02004;
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imm32 r0, 0x00000000
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[p0] = r0;
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// wrt-rd EVT2 = 0xFFE02008
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imm32 p0, 0xFFE02008
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imm32 r0, 0xE1DE5D1C
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[p0] = r0;
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// wrt-rd EVT3 = 0xFFE0200C
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imm32 p0, 0xFFE0200C
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imm32 r0, 0x9CC20332
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[p0] = r0;
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// wrt-rd EVT4 = 0xFFE02010
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imm32 p0, 0xFFE02010
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imm32 r0, 0x00000000
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[p0] = r0;
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// wrt-rd EVT5 = 0xFFE02014
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imm32 p0, 0xFFE02014
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imm32 r0, 0x55552345
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[p0] = r0;
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// wrt-rd EVT6 = 0xFFE02018
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imm32 p0, 0xFFE02018
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imm32 r0, 0x66663456
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[p0] = r0;
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// wrt-rd EVT7 = 0xFFE0201C
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imm32 p0, 0xFFE0201C
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imm32 r0, 0x77774567
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[p0] = r0;
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// wrt-rd EVT8 = 0xFFE02020
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imm32 p0, 0xFFE02020
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imm32 r0, 0x88885678
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[p0] = r0;
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// wrt-rd EVT9 = 0xFFE02024
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imm32 p0, 0xFFE02024
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imm32 r0, 0x99996789
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[p0] = r0;
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// wrt-rd EVT10 = 0xFFE02028
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imm32 p0, 0xFFE02028
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imm32 r0, 0xaaaa1234
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[p0] = r0;
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// wrt-rd EVT11 = 0xFFE0202C
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imm32 p0, 0xFFE0202C
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imm32 r0, 0xBBBBABC6
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[p0] = r0;
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// wrt-rd EVT12 = 0xFFE02030
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imm32 p0, 0xFFE02030
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imm32 r0, 0xCCCCABC6
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[p0] = r0;
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// wrt-rd EVT13 = 0xFFE02034
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imm32 p0, 0xFFE02034
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imm32 r0, 0xDDDDABC6
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[p0] = r0;
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// wrt-rd EVT14 = 0xFFE02038
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imm32 p0, 0xFFE02038
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imm32 r0, 0xEEEEABC6
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[p0] = r0;
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// wrt-rd EVT15 = 0xFFE0203C
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imm32 p0, 0xFFE0203C
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imm32 r0, 0xFFFFABC6
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[p0] = r0;
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// wrt-rd EVT_OVERRIDE:9 bits = 0xFFE02100
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imm32 p0, 0xFFE02100
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imm32 r0, 0x000001ff
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[p0] = r0;
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// wrt-rd IMASK: 16 bits = 0xFFE02104
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imm32 p0, 0xFFE02104
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imm32 r0, 0x00000fff
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[p0] = r0;
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// wrt-rd IPEND: 16 bits, rw=0 = 0xFFE02108
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imm32 p0, 0xFFE02108
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imm32 r0, 0x00000000
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//[p0] = r0;
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raise 12;
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raise 13;
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// wrt-rd ILAT: 16 bits, rw=0 = 0xFFE0210C
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imm32 p0, 0xFFE0210C
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imm32 r0, 0x00000000
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//[p0] = r0;
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csync;
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// *** read ops
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imm32 p0, 0xFFE02000
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r0 = [p0];
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CHECKREG r0, 0;
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imm32 p0, 0xFFE02004
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r1 = [p0];
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CHECKREG r1, 0;
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imm32 p0, 0xFFE02008
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r2 = [p0];
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CHECKREG r2, 0xE1DE5D1C;
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imm32 p0, 0xFFE0200C
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r3 = [p0];
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CHECKREG r3, 0x9CC20332;
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imm32 p0, 0xFFE02014
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r4 = [p0];
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imm32 p0, 0xFFE02018
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r5 = [p0];
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imm32 p0, 0xFFE0201C
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r6 = [p0];
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imm32 p0, 0xFFE02020 /* EVT8 */
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r7 = [p0];
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CHECKREG r0, 0x00000000;
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//CHECKREG(r1, 0x00000000); /// mismatch = 00
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CHECKREG r2, 0xE1DE5D1C;
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CHECKREG r3, 0x9CC20332;
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CHECKREG r4, 0x55552345;
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CHECKREG r5, 0x66663456;
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CHECKREG r6, 0x77774567;
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CHECKREG r7, 0x88885678;
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imm32 p0, 0xFFE02024 /* EVT9 */
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r0 = [p0];
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imm32 p0, 0xFFE02028 /* EVT10 */
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r1 = [p0];
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imm32 p0, 0xFFE0202C /* EVT11 */
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r2 = [p0];
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imm32 p0, 0xFFE02030 /* EVT12 */
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r3 = [p0];
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imm32 p0, 0xFFE02034 /* EVT13 */
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r4 = [p0];
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imm32 p0, 0xFFE02038 /* EVT14 */
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r5 = [p0];
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imm32 p0, 0xFFE0203C /* EVT15 */
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r6 = [p0];
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CHECKREG r0, 0x99996789;
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CHECKREG r1, 0xaaaa1234;
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CHECKREG r2, 0xBBBBABC6;
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CHECKREG r3, 0xCCCCABC6;
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CHECKREG r4, 0xDDDDABC6;
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CHECKREG r5, 0xEEEEABC6;
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CHECKREG r6, 0xFFFFABC6;
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imm32 p0, 0xFFE02100 /* EVT_OVERRIDE */
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r0 = [p0];
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imm32 p0, 0xFFE02104 /* IMASK */
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r1 = [p0];
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imm32 p0, 0xFFE02108 /* IPEND */
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r2 = [p0];
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imm32 p0, 0xFFE0210C /* ILAT */
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r3 = [p0];
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CHECKREG r0, 0x000001ff;
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CHECKREG r1, 0x00000fff; /* XXX: original had 0xfe0 ?? */
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CHECKREG r2, 0x00008000;
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CHECKREG r3, 0x00003000;
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dbg_pass;
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// *********************************************************************
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//
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// Handlers for Events
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//
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EHANDLE: // Emulation Handler 0
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RTE;
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RHANDLE: // Reset Handler 1
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RTI;
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NHANDLE: // NMI Handler 2
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r0 = 2;
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RTN;
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XHANDLE: // Exception Handler 3
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RTX;
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HWHANDLE: // HW Error Handler 5
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r2 = 5;
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RTI;
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THANDLE: // Timer Handler 6
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r3 = 6;
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RTI;
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I7HANDLE: // IVG 7 Handler
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r4 = 7;
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RTI;
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I8HANDLE: // IVG 8 Handler
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r5 = 8;
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RTI;
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I9HANDLE: // IVG 9 Handler
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r6 = 9;
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RTI;
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I10HANDLE: // IVG 10 Handler
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r7 = 10;
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RTI;
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I11HANDLE: // IVG 11 Handler
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r0 = 11;
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RTI;
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I12HANDLE: // IVG 12 Handler
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r1 = 12;
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RTI;
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I13HANDLE: // IVG 13 Handler
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r2 = 13;
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RTI;
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I14HANDLE: // IVG 14 Handler
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r3 = 14;
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RTI;
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I15HANDLE: // IVG 15 Handler
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r4 = 15;
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RTI;
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nop;nop;nop;nop;nop;nop;nop; // needed for icache bug
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//
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// Data Segment
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//
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.data
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// Stack Segments (Both Kernel and User)
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.rep 0x10
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.byte 0
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.endr
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KSTACK:
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.rep 0x10
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.byte 0
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.endr
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USTACK:
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