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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
168 lines
2.9 KiB
ArmAsm
168 lines
2.9 KiB
ArmAsm
//Original:/testcases/core/c_loopsetup_overlap/c_loopsetup_overlap.dsp
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// Spec Reference: loopsetup overlap
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# mach: bfin
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.include "testutils.inc"
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start
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INIT_R_REGS 0;
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ASTAT = r0;
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//p0 = 2;
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P1 = 3;
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P2 = 4;
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P3 = 5;
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P4 = 6;
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P5 = 7;
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SP = 8;
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FP = 9;
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R0 = 0x05;
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R1 = 0x10;
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R2 = 0x20;
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R3 = 0x30;
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R4 = 0x40 (X);
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R5 = 0x50 (X);
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R6 = 0x60 (X);
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R7 = 0x70 (X);
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LSETUP ( start1 , end1 ) LC0 = P1;
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start1: R0 += 1;
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R1 += -2;
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LSETUP ( start2 , end2 ) LC1 = P2;
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start2: R4 += 4;
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end2: R5 += -5;
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R3 += 1;
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end1: R2 += 3;
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R3 += 4;
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LSETUP ( start3 , end3 ) LC1 = P3;
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start3: R6 += 6;
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LSETUP ( start4 , end4 ) LC0 = P4 >> 1;
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start4: R0 += 1;
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R1 += -2;
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end3: R2 += 3;
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R3 += 4;
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end4: R7 += -7;
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R3 += 1;
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CHECKREG r0, 0x0000000F;
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CHECKREG r1, 0xFFFFFFFC;
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CHECKREG r2, 0x0000003E;
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CHECKREG r3, 0x00000044;
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CHECKREG r4, 0x00000070;
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CHECKREG r5, 0x00000014;
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CHECKREG r6, 0x0000007E;
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CHECKREG r7, 0x0000005B;
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R0 = 0x05;
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R1 = 0x10;
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R2 = 0x20;
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R3 = 0x30;
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R4 = 0x40 (X);
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R5 = 0x50 (X);
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R6 = 0x60 (X);
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R7 = 0x70 (X);
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LSETUP ( start5 , end5 ) LC0 = P5;
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start5: R4 += 1;
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LSETUP ( start6 , end6 ) LC1 = SP >> 1;
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start6: R6 += 4;
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end5: R7 += -5;
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R3 += 6;
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end6: R5 += -2;
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R3 += 3;
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CHECKREG r0, 0x00000005;
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CHECKREG r1, 0x00000010;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x0000004B;
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CHECKREG r4, 0x00000047;
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CHECKREG r5, 0x00000048;
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CHECKREG r6, 0x00000088;
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CHECKREG r7, 0x0000003E;
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LSETUP ( start7 , end7 ) LC0 = FP;
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start7: R4 += 4;
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end7: R5 += -5;
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R3 += 6;
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CHECKREG r0, 0x00000005;
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CHECKREG r1, 0x00000010;
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CHECKREG r2, 0x00000020;
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CHECKREG r3, 0x00000051;
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CHECKREG r4, 0x0000006B;
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CHECKREG r5, 0x0000001B;
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CHECKREG r6, 0x00000088;
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CHECKREG r7, 0x0000003E;
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P1 = 8;
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P2 = 10;
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P3 = 12;
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P4 = 14;
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P5 = 16;
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SP = 18;
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FP = 20;
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R0 = 0x05;
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R1 = 0x10;
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R2 = 0x20;
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R3 = 0x30;
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R4 = 0x40 (X);
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R5 = 0x50 (X);
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R6 = 0x60 (X);
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R7 = 0x70 (X);
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LSETUP ( start11 , end11 ) LC1 = P1;
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start11: R0 += 1;
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R1 += -1;
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LSETUP ( start15 , end15 ) LC0 = P5;
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start15: R4 += 5;
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end11: R5 += -14;
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R3 += 1;
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end15: R2 += 17;
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R3 += 12;
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LSETUP ( start13 , end13 ) LC1 = P3;
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start13: R6 += 1;
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LSETUP ( start12 , end12 ) LC0 = P2;
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start12: R4 += 22;
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end13: R5 += -11;
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R3 += 13;
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end12: R7 += -1;
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R3 += 14;
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CHECKREG r0, 0x0000000D;
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CHECKREG r1, 0x00000008;
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CHECKREG r2, 0x00000130;
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CHECKREG r3, 0x000000DC;
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CHECKREG r4, 0x00000281;
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CHECKREG r5, 0xFFFFFE27;
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CHECKREG r6, 0x0000006C;
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CHECKREG r7, 0x00000066;
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R0 = 0x05;
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R1 = 0x10;
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R2 = 0x20;
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R3 = 0x30;
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R4 = 0x40 (X);
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R5 = 0x50 (X);
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R6 = 0x60 (X);
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R7 = 0x70 (X);
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LSETUP ( start14 , end14 ) LC0 = P4;
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start14: R0 += 21;
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R1 += -11;
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LSETUP ( start16 , end16 ) LC1 = SP;
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start16: R6 += 10;
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end16: R7 += -12;
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R3 += 1;
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LSETUP ( start17 , end17 ) LC1 = FP >> 1;
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start17: R4 += 31;
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end14: R5 += -1;
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R3 += 11;
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end17: R2 += 41;
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R3 += 1;
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CHECKREG r0, 0x0000012B;
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CHECKREG r1, 0xFFFFFF76;
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CHECKREG r2, 0x000001BA;
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CHECKREG r3, 0x000000AD;
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CHECKREG r4, 0x00000309;
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CHECKREG r5, 0x00000039;
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CHECKREG r6, 0x00000A38;
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CHECKREG r7, 0xFFFFF4A0;
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pass
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