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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
214 lines
4.1 KiB
ArmAsm
214 lines
4.1 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_a0alr/c_dsp32shiftim_a0alr.dsp
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// Spec Reference: dsp32shift a0 ashift, lshift, rot
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# mach: bfin
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.include "testutils.inc"
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start
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R0 = 0;
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ASTAT = R0;
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imm32 r0, 0x11140000;
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imm32 r1, 0x012C003E;
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imm32 r2, 0x81359E24;
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imm32 r3, 0x81459E24;
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imm32 r4, 0xD159E268;
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imm32 r5, 0x51626AF2;
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imm32 r6, 0x9176AF36;
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imm32 r7, 0xE18BFF86;
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R0.L = 0;
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A0 = 0;
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A0.L = R1.L;
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A0.H = R1.H;
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A0 = A0 << 0; /* a0 = 0x00000000 */
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R1 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r1, 0x012C003E;
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R1.L = 1;
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A0.L = R2.L;
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A0.H = R2.H;
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A0 = A0 << 1; /* a0 = 0x00000000 */
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R2 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r2, 0x026B3C48;
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R2.L = 15;
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A0.L = R3.L;
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A0.H = R3.H;
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A0 = A0 << 15; /* a0 = 0x00000000 */
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R3 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r3, 0xCF120000;
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R3.L = 31;
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A0.L = R4.L;
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A0.H = R4.H;
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A0 = A0 << 31; /* a0 = 0x00000000 */
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R4 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r4, 0x00000000;
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R4.L = -1;
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A0.L = R5.L;
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A0.H = R5.H;
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A0 = A0 >>> 1; /* a0 = 0x00000000 */
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R5 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r5, 0x28B13579;
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R5.L = -16;
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A0 = 0;
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A0.L = R6.L;
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A0.H = R6.H;
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A0 = A0 >>> 16; /* a0 = 0x00000000 */
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R6 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r6, 0x00009176;
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R6.L = -31;
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A0.L = R7.L;
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A0.H = R7.H;
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A0 = A0 >>> 31; /* a0 = 0x00000000 */
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R0 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r0, 0x00000001;
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R7.L = -32;
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A0.L = R0.L;
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A0.H = R0.H;
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.dw 0xC683 // .dw 0xC683 // A0 = A0 >>> 32;
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.dw 0x0100
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R7 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r7, 0x00000000;
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imm32 r0, 0x12340000;
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imm32 r1, 0x028C003E;
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imm32 r2, 0x82159E24;
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imm32 r3, 0x82159E24;
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imm32 r4, 0xD259E268;
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imm32 r5, 0x52E26AF2;
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imm32 r6, 0x9226AF36;
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imm32 r7, 0xE26BFF86;
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R0.L = 0;
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A0 = 0;
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A0.L = R1.L;
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A0.H = R1.H;
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A0 = A0 << 0; /* a0 = 0x00000000 */
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R1 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r1, 0x028C003E;
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R1.L = 1;
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A0.L = R2.L;
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A0.H = R2.H;
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A0 = A0 << 3; /* a0 = 0x00000000 */
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R2 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r2, 0x10ACF120;
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R2.L = 15;
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A0.L = R3.L;
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A0.H = R3.H;
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A0 = A0 << 15; /* a0 = 0x00000000 */
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R3 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r3, 0xCF120000;
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R3.L = 31;
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A0.L = R4.L;
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A0.H = R4.H;
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A0 = A0 << 31; /* a0 = 0x00000000 */
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R4 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r4, 0x00000000;
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R4.L = -1;
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A0.L = R5.L;
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A0.H = R5.H;
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A0 = A0 >> 1; /* a0 = 0x00000000 */
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R5 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r5, 0x29713579;
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R5.L = -16;
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A0 = 0;
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A0.L = R6.L;
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A0.H = R6.H;
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A0 = A0 >> 16; /* a0 = 0x00000000 */
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R6 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r6, 0x00009226;
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R6.L = -31;
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A0.L = R7.L;
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A0.H = R7.H;
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A0 = A0 >> 31; /* a0 = 0x00000000 */
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R7 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r7, 0x00000001;
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R7.L = -32;
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A0.L = R0.L;
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A0.H = R0.H;
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.dw 0xC683
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.dw 0x4100 // A0 = A0 >> 32;
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R0 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r0, 0x00000000;
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imm32 r0, 0x13340000;
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imm32 r1, 0x038C003E;
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imm32 r2, 0x83159E24;
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imm32 r3, 0x83159E24;
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imm32 r4, 0xD359E268;
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imm32 r5, 0x53E26AF2;
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imm32 r6, 0x9326AF36;
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imm32 r7, 0xE36BFF86;
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R0.L = 0;
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A0 = 0;
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A0.L = R1.L;
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A0.H = R1.H;
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A0 = ROT A0 BY 0; /* a0 = 0x00000000 */
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R1 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r1, 0x038C003E;
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R1.L = 1;
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A0.L = R2.L;
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A0.H = R2.H;
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A0 = ROT A0 BY 1; /* a0 = 0x00000000 */
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R2 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r2, 0x062B3C48;
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R2.L = 15;
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A0.L = R3.L;
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A0.H = R3.H;
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A0 = ROT A0 BY 15; /* a0 = 0x00000000 */
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R3 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r3, 0xCF120060;
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R3.L = 31;
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A0.L = R4.L;
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A0.H = R4.H;
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A0 = ROT A0 BY 31; /* a0 = 0x00000000 */
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R4 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r4, 0x62B4D678;
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R4.L = -1;
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A0.L = R5.L;
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A0.H = R5.H;
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A0 = ROT A0 BY -1; /* a0 = 0x00000000 */
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R5 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r5, 0x29F13579;
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R5.L = -16;
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A0.L = R6.L;
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A0.H = R6.H;
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A0 = ROT A0 BY -16; /* a0 = 0x00000000 */
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R6 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r6, 0x6C9A9326;
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R6.L = -31;
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A0.L = R7.L;
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A0.H = R7.H;
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A0 = ROT A0 BY -31; /* a0 = 0x00000000 */
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R7 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r7, 0xAFFE1ABD;
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R7.L = -32;
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A0.L = R0.L;
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A0.H = R0.H;
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A0 = ROT A0 BY -32; /* a0 = 0x00000000 */
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R0 = A0.w; /* r5 = 0x00000000 */
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CHECKREG r0, 0x6800018D;
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pass
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