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74bbe64132
Now that we require C11, we can leverage anonymous unions & structs to fix a long standing issue with the SH register layout. The use of sregs.i for sh-dsp has generated a lot of compiler warnings about the access being out of bounds -- it only has 7 elements declared, but code goes beyond that to reach into the fregs that follow. But now that we have anonymous unions, we can reduce the nested names and have sregs cover all of these registers.
127 lines
2.7 KiB
C
127 lines
2.7 KiB
C
/* Moxie Simulator definition.
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Copyright (C) 2009-2021 Free Software Foundation, Inc.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef SIM_MAIN_H
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#define SIM_MAIN_H
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#include "sim-basics.h"
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#include "sim-base.h"
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typedef struct
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{
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int regs[20];
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} regstacktype;
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typedef union
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{
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struct
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{
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int regs[16];
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int pc;
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/* System registers. For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
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which are located in fregs. Probably should include pc too - to avoid
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alignment repercussions. */
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union {
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struct {
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int mach;
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int macl;
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int pr;
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int dummy3, dummy4;
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int fpul; /* A1 for sh-dsp - but only for movs etc. */
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int fpscr; /* dsr for sh-dsp */
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/* sh3e / sh-dsp */
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union fregs_u {
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float f[16];
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double d[8];
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int i[16];
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} fregs[2];
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};
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int sregs[39];
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};
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/* Control registers; on the SH4, ldc / stc is privileged, except when
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accessing gbr. */
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union
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{
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struct
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{
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int sr;
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int gbr;
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int vbr;
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int ssr;
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int spc;
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int mod;
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/* sh-dsp */
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int rs;
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int re;
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/* sh3 */
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int bank[8];
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int dbr; /* debug base register */
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int sgr; /* saved gr15 */
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int ldst; /* load/store flag (boolean) */
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int tbr;
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int ibcr; /* sh2a bank control register */
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int ibnr; /* sh2a bank number register */
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};
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int cregs[16];
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};
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unsigned char *insn_end;
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int ticks;
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int stalls;
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int memstalls;
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int cycles;
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int insts;
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int prevlock;
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int thislock;
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int exception;
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int end_of_registers;
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int msize;
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#define PROFILE_FREQ 1
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#define PROFILE_SHIFT 2
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int profile;
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unsigned short *profile_hist;
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unsigned char *memory;
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int xyram_select, xram_start, yram_start;
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unsigned char *xmem;
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unsigned char *ymem;
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unsigned char *xmem_offset;
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unsigned char *ymem_offset;
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unsigned long bfd_mach;
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regstacktype *regstack;
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} asregs;
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int asints[40];
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} saved_state_type;
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/* TODO: Move into sim_cpu. */
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extern saved_state_type saved_state;
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struct _sim_cpu {
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sim_cpu_base base;
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};
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#endif
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