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6df01ab8ab
The defs.h header will take care of including the various config.h headers. For now, it's just config.h, but we'll add more when we integrate gnulib in. This header should be used instead of config.h, and should be the first include in every .c file. We won't rely on the old behavior where we expected files to include the port's sim-main.h which then includes the common sim-basics.h which then includes config.h. We have a ton of code that includes things before sim-main.h, and it sometimes needs to be that way. Creating a dedicated header avoids the ordering mess and implicit inclusion that shows up otherwise.
356 lines
10 KiB
C
356 lines
10 KiB
C
/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#include <string.h>
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#include "armdefs.h"
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#include "armemu.h"
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#include "dbg_rdi.h"
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/***************************************************************************\
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* Definitions for the emulator architecture *
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\***************************************************************************/
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void ARMul_EmulateInit (void);
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ARMul_State *ARMul_NewState (void);
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void ARMul_Reset (ARMul_State * state);
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ARMword ARMul_DoCycle (ARMul_State * state);
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unsigned ARMul_DoCoPro (ARMul_State * state);
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ARMword ARMul_DoProg (ARMul_State * state);
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ARMword ARMul_DoInstr (ARMul_State * state);
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void ARMul_Abort (ARMul_State * state, ARMword address);
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unsigned ARMul_MultTable[32] =
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{ 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9,
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10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16
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};
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ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */
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char ARMul_BitList[256]; /* number of bits in a byte table */
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/* The PC pipeline value depends on whether ARM
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or Thumb instructions are being executed. */
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ARMword isize;
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/***************************************************************************\
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* Call this routine once to set up the emulator's tables. *
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\***************************************************************************/
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void
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ARMul_EmulateInit (void)
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{
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unsigned long i, j;
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for (i = 0; i < 4096; i++)
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{ /* the values of 12 bit dp rhs's */
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ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL);
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}
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for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */
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for (j = 1; j < 256; j <<= 1)
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for (i = 0; i < 256; i++)
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if ((i & j) > 0)
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ARMul_BitList[i]++;
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for (i = 0; i < 256; i++)
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ARMul_BitList[i] *= 4; /* you always need 4 times these values */
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}
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/***************************************************************************\
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* Returns a new instantiation of the ARMulator's state *
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\***************************************************************************/
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ARMul_State *
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ARMul_NewState (void)
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{
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ARMul_State *state;
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unsigned i, j;
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state = (ARMul_State *) malloc (sizeof (ARMul_State));
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memset (state, 0, sizeof (ARMul_State));
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state->Emulate = RUN;
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for (i = 0; i < 16; i++)
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{
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state->Reg[i] = 0;
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for (j = 0; j < 7; j++)
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state->RegBank[j][i] = 0;
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}
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for (i = 0; i < 7; i++)
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state->Spsr[i] = 0;
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/* state->Mode = USER26MODE; */
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state->Mode = USER32MODE;
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state->CallDebug = FALSE;
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state->Debug = FALSE;
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state->VectorCatch = 0;
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state->Aborted = FALSE;
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state->Reseted = FALSE;
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state->Inted = 3;
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state->LastInted = 3;
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state->MemDataPtr = NULL;
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state->MemInPtr = NULL;
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state->MemOutPtr = NULL;
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state->MemSparePtr = NULL;
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state->MemSize = 0;
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state->OSptr = NULL;
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state->CommandLine = NULL;
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state->CP14R0_CCD = -1;
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state->LastTime = 0;
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state->EventSet = 0;
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state->Now = 0;
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state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE *
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sizeof (struct EventNode
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*));
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for (i = 0; i < EVENTLISTSIZE; i++)
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*(state->EventPtr + i) = NULL;
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state->prog32Sig = HIGH;
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state->data32Sig = HIGH;
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state->lateabtSig = LOW;
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state->bigendSig = LOW;
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state->is_v4 = LOW;
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state->is_v5 = LOW;
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state->is_v5e = LOW;
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state->is_XScale = LOW;
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state->is_iWMMXt = LOW;
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state->is_v6 = LOW;
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ARMul_Reset (state);
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return state;
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}
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/***************************************************************************\
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Call this routine to set ARMulator to model certain processor properities
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\***************************************************************************/
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void
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ARMul_SelectProcessor (ARMul_State * state, unsigned properties)
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{
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if (properties & ARM_Fix26_Prop)
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{
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state->prog32Sig = LOW;
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state->data32Sig = LOW;
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}
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else
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{
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state->prog32Sig = HIGH;
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state->data32Sig = HIGH;
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}
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state->lateabtSig = LOW;
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state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW;
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state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW;
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state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW;
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state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW;
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state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW;
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state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW;
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state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW;
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/* Only initialse the coprocessor support once we
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know what kind of chip we are dealing with. */
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ARMul_CoProInit (state);
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}
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/***************************************************************************\
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* Call this routine to set up the initial machine state (or perform a RESET *
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\***************************************************************************/
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void
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ARMul_Reset (ARMul_State * state)
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{
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state->NextInstr = 0;
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if (state->prog32Sig)
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{
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state->Reg[15] = 0;
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state->Cpsr = INTBITS | SVC32MODE;
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state->Mode = SVC32MODE;
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}
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else
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{
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state->Reg[15] = R15INTBITS | SVC26MODE;
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state->Cpsr = INTBITS | SVC26MODE;
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state->Mode = SVC26MODE;
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}
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ARMul_CPSRAltered (state);
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state->Bank = SVCBANK;
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FLUSHPIPE;
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state->EndCondition = 0;
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state->Exception = FALSE;
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state->NresetSig = HIGH;
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state->NfiqSig = HIGH;
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state->NirqSig = HIGH;
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state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
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state->abortSig = LOW;
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state->AbortAddr = 1;
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state->NumInstrs = 0;
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state->NumNcycles = 0;
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state->NumScycles = 0;
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state->NumIcycles = 0;
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state->NumCcycles = 0;
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state->NumFcycles = 0;
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#ifdef ASIM
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(void) ARMul_MemoryInit ();
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ARMul_OSInit (state);
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#endif
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}
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/***************************************************************************\
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* Emulate the execution of an entire program. Start the correct emulator *
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* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
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* address of the last instruction that is executed. *
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\***************************************************************************/
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ARMword
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ARMul_DoProg (ARMul_State * state)
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{
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ARMword pc = 0;
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state->Emulate = RUN;
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while (state->Emulate != STOP)
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{
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state->Emulate = RUN;
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if (state->prog32Sig && ARMul_MODE32BIT)
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pc = ARMul_Emulate32 (state);
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else
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pc = ARMul_Emulate26 (state);
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}
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return (pc);
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}
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/***************************************************************************\
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* Emulate the execution of one instruction. Start the correct emulator *
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* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
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* address of the instruction that is executed. *
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\***************************************************************************/
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ARMword
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ARMul_DoInstr (ARMul_State * state)
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{
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ARMword pc = 0;
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state->Emulate = ONCE;
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if (state->prog32Sig && ARMul_MODE32BIT)
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pc = ARMul_Emulate32 (state);
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else
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pc = ARMul_Emulate26 (state);
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return (pc);
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}
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/***************************************************************************\
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* This routine causes an Abort to occur, including selecting the correct *
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* mode, register bank, and the saving of registers. Call with the *
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* appropriate vector's memory address (0,4,8 ....) *
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\***************************************************************************/
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void
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ARMul_Abort (ARMul_State * state, ARMword vector)
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{
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ARMword temp;
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int isize = INSN_SIZE;
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int esize = (TFLAG ? 0 : 4);
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int e2size = (TFLAG ? -4 : 0);
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state->Aborted = FALSE;
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if (state->prog32Sig)
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if (ARMul_MODE26BIT)
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temp = R15PC;
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else
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temp = state->Reg[15];
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else
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temp = R15PC | ECC | ER15INT | EMODE;
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switch (vector)
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{
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case ARMul_ResetV: /* RESET */
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SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 0);
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break;
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case ARMul_UndefinedInstrV: /* Undefined Instruction */
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SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, isize);
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break;
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case ARMul_SWIV: /* Software Interrupt */
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SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, isize);
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break;
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case ARMul_PrefetchAbortV: /* Prefetch Abort */
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state->AbortAddr = 1;
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SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, esize);
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break;
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case ARMul_DataAbortV: /* Data Abort */
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SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, e2size);
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break;
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case ARMul_AddrExceptnV: /* Address Exception */
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SETABORT (IBIT, SVC26MODE, isize);
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break;
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case ARMul_IRQV: /* IRQ */
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if ( ! state->is_XScale
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|| ! state->CPRead[13] (state, 0, & temp)
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|| (temp & ARMul_CP13_R0_IRQ))
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SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize);
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break;
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case ARMul_FIQV: /* FIQ */
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if ( ! state->is_XScale
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|| ! state->CPRead[13] (state, 0, & temp)
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|| (temp & ARMul_CP13_R0_FIQ))
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SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize);
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break;
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}
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if (ARMul_MODE32BIT)
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ARMul_SetR15 (state, vector);
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else
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ARMul_SetR15 (state, R15CCINTMODE | vector);
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if (ARMul_ReadWord (state, ARMul_GetPC (state)) == 0)
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{
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/* No vector has been installed. Rather than simulating whatever
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random bits might happen to be at address 0x20 onwards we elect
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to stop. */
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switch (vector)
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{
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case ARMul_ResetV: state->EndCondition = RDIError_Reset; break;
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case ARMul_UndefinedInstrV: state->EndCondition = RDIError_UndefinedInstruction; break;
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case ARMul_SWIV: state->EndCondition = RDIError_SoftwareInterrupt; break;
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case ARMul_PrefetchAbortV: state->EndCondition = RDIError_PrefetchAbort; break;
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case ARMul_DataAbortV: state->EndCondition = RDIError_DataAbort; break;
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case ARMul_AddrExceptnV: state->EndCondition = RDIError_AddressException; break;
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case ARMul_IRQV: state->EndCondition = RDIError_IRQ; break;
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case ARMul_FIQV: state->EndCondition = RDIError_FIQ; break;
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default: break;
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}
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state->Emulate = FALSE;
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}
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}
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