mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-21 04:42:53 +08:00
1fef66b0dc
The sim-basics.h is too big and includes too many things. This leads to some arch's sim-main.h having circular loop issues with defs, and makes it hard to separate out common objects from arch-specific defs. By splitting up sim-basics.h and killing off sim-main.h, it'll make it easier to separate out the two.
646 lines
14 KiB
C
646 lines
14 KiB
C
/* cpustate.h -- Prototypes for AArch64 simulator functions.
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Copyright (C) 2015-2021 Free Software Foundation, Inc.
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Contributed by Red Hat.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#include <stdio.h>
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#include <math.h>
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#include "sim-main.h"
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#include "sim-signal.h"
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#include "cpustate.h"
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#include "simulator.h"
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#include "libiberty.h"
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/* Some operands are allowed to access the stack pointer (reg 31).
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For others a read from r31 always returns 0, and a write to r31 is ignored. */
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#define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg))
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void
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aarch64_set_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint64_t val)
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{
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if (reg == R31 && ! r31_is_sp)
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{
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TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
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return;
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}
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if (val != cpu->gr[reg].u64)
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TRACE_REGISTER (cpu,
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"GR[%2d] changes from %16" PRIx64 " to %16" PRIx64,
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reg, cpu->gr[reg].u64, val);
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cpu->gr[reg].u64 = val;
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}
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void
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aarch64_set_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp, int64_t val)
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{
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if (reg == R31 && ! r31_is_sp)
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{
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TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
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return;
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}
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if (val != cpu->gr[reg].s64)
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TRACE_REGISTER (cpu,
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"GR[%2d] changes from %16" PRIx64 " to %16" PRIx64,
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reg, cpu->gr[reg].s64, val);
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cpu->gr[reg].s64 = val;
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}
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uint64_t
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aarch64_get_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp)
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{
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return cpu->gr[reg_num(reg)].u64;
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}
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int64_t
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aarch64_get_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp)
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{
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return cpu->gr[reg_num(reg)].s64;
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}
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uint32_t
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aarch64_get_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp)
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{
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return cpu->gr[reg_num(reg)].u32;
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}
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int32_t
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aarch64_get_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp)
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{
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return cpu->gr[reg_num(reg)].s32;
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}
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void
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aarch64_set_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp, int32_t val)
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{
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if (reg == R31 && ! r31_is_sp)
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{
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TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
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return;
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}
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if (val != cpu->gr[reg].s32)
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TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x",
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reg, cpu->gr[reg].s32, val);
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/* The ARM ARM states that (C1.2.4):
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When the data size is 32 bits, the lower 32 bits of the
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register are used and the upper 32 bits are ignored on
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a read and cleared to zero on a write.
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We simulate this by first clearing the whole 64-bits and
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then writing to the 32-bit value in the GRegister union. */
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cpu->gr[reg].s64 = 0;
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cpu->gr[reg].s32 = val;
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}
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void
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aarch64_set_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint32_t val)
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{
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if (reg == R31 && ! r31_is_sp)
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{
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TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
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return;
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}
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if (val != cpu->gr[reg].u32)
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TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x",
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reg, cpu->gr[reg].u32, val);
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cpu->gr[reg].u64 = 0;
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cpu->gr[reg].u32 = val;
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}
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uint32_t
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aarch64_get_reg_u16 (sim_cpu *cpu, GReg reg, int r31_is_sp)
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{
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return cpu->gr[reg_num(reg)].u16;
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}
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int32_t
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aarch64_get_reg_s16 (sim_cpu *cpu, GReg reg, int r31_is_sp)
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{
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return cpu->gr[reg_num(reg)].s16;
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}
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uint32_t
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aarch64_get_reg_u8 (sim_cpu *cpu, GReg reg, int r31_is_sp)
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{
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return cpu->gr[reg_num(reg)].u8;
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}
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int32_t
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aarch64_get_reg_s8 (sim_cpu *cpu, GReg reg, int r31_is_sp)
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{
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return cpu->gr[reg_num(reg)].s8;
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}
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uint64_t
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aarch64_get_PC (sim_cpu *cpu)
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{
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return cpu->pc;
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}
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uint64_t
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aarch64_get_next_PC (sim_cpu *cpu)
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{
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return cpu->nextpc;
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}
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void
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aarch64_set_next_PC (sim_cpu *cpu, uint64_t next)
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{
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if (next != cpu->nextpc + 4)
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TRACE_REGISTER (cpu,
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"NextPC changes from %16" PRIx64 " to %16" PRIx64,
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cpu->nextpc, next);
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cpu->nextpc = next;
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}
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void
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aarch64_set_next_PC_by_offset (sim_cpu *cpu, int64_t offset)
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{
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if (cpu->pc + offset != cpu->nextpc + 4)
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TRACE_REGISTER (cpu,
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"NextPC changes from %16" PRIx64 " to %16" PRIx64,
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cpu->nextpc, cpu->pc + offset);
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cpu->nextpc = cpu->pc + offset;
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}
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/* Install nextpc as current pc. */
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void
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aarch64_update_PC (sim_cpu *cpu)
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{
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cpu->pc = cpu->nextpc;
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/* Rezero the register we hand out when asked for ZR just in case it
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was used as the destination for a write by the previous
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instruction. */
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cpu->gr[32].u64 = 0UL;
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}
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/* This instruction can be used to save the next PC to LR
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just before installing a branch PC. */
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void
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aarch64_save_LR (sim_cpu *cpu)
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{
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if (cpu->gr[LR].u64 != cpu->nextpc)
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TRACE_REGISTER (cpu,
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"LR changes from %16" PRIx64 " to %16" PRIx64,
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cpu->gr[LR].u64, cpu->nextpc);
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cpu->gr[LR].u64 = cpu->nextpc;
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}
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static const char *
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decode_cpsr (FlagMask flags)
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{
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switch (flags & CPSR_ALL_FLAGS)
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{
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default:
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case 0: return "----";
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case 1: return "---V";
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case 2: return "--C-";
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case 3: return "--CV";
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case 4: return "-Z--";
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case 5: return "-Z-V";
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case 6: return "-ZC-";
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case 7: return "-ZCV";
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case 8: return "N---";
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case 9: return "N--V";
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case 10: return "N-C-";
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case 11: return "N-CV";
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case 12: return "NZ--";
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case 13: return "NZ-V";
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case 14: return "NZC-";
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case 15: return "NZCV";
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}
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}
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/* Retrieve the CPSR register as an int. */
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uint32_t
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aarch64_get_CPSR (sim_cpu *cpu)
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{
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return cpu->CPSR;
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}
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/* Set the CPSR register as an int. */
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void
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aarch64_set_CPSR (sim_cpu *cpu, uint32_t new_flags)
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{
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if (TRACE_REGISTER_P (cpu))
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{
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if (cpu->CPSR != new_flags)
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TRACE_REGISTER (cpu,
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"CPSR changes from %s to %s",
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decode_cpsr (cpu->CPSR), decode_cpsr (new_flags));
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else
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TRACE_REGISTER (cpu,
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"CPSR stays at %s", decode_cpsr (cpu->CPSR));
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}
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cpu->CPSR = new_flags & CPSR_ALL_FLAGS;
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}
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/* Read a specific subset of the CPSR as a bit pattern. */
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uint32_t
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aarch64_get_CPSR_bits (sim_cpu *cpu, FlagMask mask)
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{
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return cpu->CPSR & mask;
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}
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/* Assign a specific subset of the CPSR as a bit pattern. */
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void
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aarch64_set_CPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value)
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{
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uint32_t old_flags = cpu->CPSR;
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mask &= CPSR_ALL_FLAGS;
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cpu->CPSR &= ~ mask;
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cpu->CPSR |= (value & mask);
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if (old_flags != cpu->CPSR)
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TRACE_REGISTER (cpu,
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"CPSR changes from %s to %s",
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decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
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}
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/* Test the value of a single CPSR returned as non-zero or zero. */
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uint32_t
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aarch64_test_CPSR_bit (sim_cpu *cpu, FlagMask bit)
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{
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return cpu->CPSR & bit;
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}
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/* Set a single flag in the CPSR. */
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void
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aarch64_set_CPSR_bit (sim_cpu *cpu, FlagMask bit)
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{
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uint32_t old_flags = cpu->CPSR;
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cpu->CPSR |= (bit & CPSR_ALL_FLAGS);
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if (old_flags != cpu->CPSR)
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TRACE_REGISTER (cpu,
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"CPSR changes from %s to %s",
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decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
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}
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/* Clear a single flag in the CPSR. */
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void
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aarch64_clear_CPSR_bit (sim_cpu *cpu, FlagMask bit)
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{
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uint32_t old_flags = cpu->CPSR;
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cpu->CPSR &= ~(bit & CPSR_ALL_FLAGS);
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if (old_flags != cpu->CPSR)
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TRACE_REGISTER (cpu,
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"CPSR changes from %s to %s",
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decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
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}
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float
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aarch64_get_FP_half (sim_cpu *cpu, VReg reg)
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{
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union
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{
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uint16_t h[2];
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float f;
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} u;
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u.h[0] = 0;
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u.h[1] = cpu->fr[reg].h[0];
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return u.f;
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}
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float
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aarch64_get_FP_float (sim_cpu *cpu, VReg reg)
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{
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return cpu->fr[reg].s;
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}
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double
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aarch64_get_FP_double (sim_cpu *cpu, VReg reg)
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{
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return cpu->fr[reg].d;
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}
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void
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aarch64_get_FP_long_double (sim_cpu *cpu, VReg reg, FRegister *a)
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{
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a->v[0] = cpu->fr[reg].v[0];
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a->v[1] = cpu->fr[reg].v[1];
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}
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void
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aarch64_set_FP_half (sim_cpu *cpu, VReg reg, float val)
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{
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union
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{
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uint16_t h[2];
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float f;
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} u;
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u.f = val;
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cpu->fr[reg].h[0] = u.h[1];
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cpu->fr[reg].h[1] = 0;
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}
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void
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aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val)
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{
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if (val != cpu->fr[reg].s
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/* Handle +/- zero. */
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|| signbit (val) != signbit (cpu->fr[reg].s))
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{
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FRegister v;
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v.s = val;
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TRACE_REGISTER (cpu,
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"FR[%d].s changes from %f to %f [hex: %0" PRIx64 "]",
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reg, cpu->fr[reg].s, val, v.v[0]);
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}
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cpu->fr[reg].s = val;
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}
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void
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aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val)
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{
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if (val != cpu->fr[reg].d
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/* Handle +/- zero. */
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|| signbit (val) != signbit (cpu->fr[reg].d))
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{
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FRegister v;
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v.d = val;
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TRACE_REGISTER (cpu,
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"FR[%d].d changes from %f to %f [hex: %0" PRIx64 "]",
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reg, cpu->fr[reg].d, val, v.v[0]);
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}
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cpu->fr[reg].d = val;
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}
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void
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aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a)
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{
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if (cpu->fr[reg].v[0] != a.v[0]
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|| cpu->fr[reg].v[1] != a.v[1])
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TRACE_REGISTER (cpu,
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"FR[%d].q changes from [%0" PRIx64 " %0" PRIx64 "] to [%0"
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PRIx64 " %0" PRIx64 "] ",
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reg,
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cpu->fr[reg].v[0], cpu->fr[reg].v[1],
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a.v[0], a.v[1]);
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cpu->fr[reg].v[0] = a.v[0];
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cpu->fr[reg].v[1] = a.v[1];
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}
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#define GET_VEC_ELEMENT(REG, ELEMENT, FIELD) \
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do \
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{ \
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if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
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{ \
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TRACE_REGISTER (cpu, \
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"Internal SIM error: invalid element number: %d ",\
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ELEMENT); \
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sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
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sim_stopped, SIM_SIGBUS); \
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} \
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return cpu->fr[REG].FIELD [ELEMENT]; \
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} \
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while (0)
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uint64_t
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aarch64_get_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element)
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{
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GET_VEC_ELEMENT (reg, element, v);
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}
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uint32_t
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aarch64_get_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element)
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{
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GET_VEC_ELEMENT (reg, element, w);
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}
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uint16_t
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aarch64_get_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element)
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{
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GET_VEC_ELEMENT (reg, element, h);
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}
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uint8_t
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aarch64_get_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element)
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{
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GET_VEC_ELEMENT (reg, element, b);
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}
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int64_t
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aarch64_get_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element)
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{
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GET_VEC_ELEMENT (reg, element, V);
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}
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int32_t
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aarch64_get_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element)
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{
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GET_VEC_ELEMENT (reg, element, W);
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}
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int16_t
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aarch64_get_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element)
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{
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GET_VEC_ELEMENT (reg, element, H);
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}
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int8_t
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aarch64_get_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element)
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{
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GET_VEC_ELEMENT (reg, element, B);
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}
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float
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aarch64_get_vec_float (sim_cpu *cpu, VReg reg, unsigned element)
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{
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GET_VEC_ELEMENT (reg, element, S);
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}
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double
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aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element)
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{
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GET_VEC_ELEMENT (reg, element, D);
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}
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#define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER) \
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do \
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{ \
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if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
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{ \
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TRACE_REGISTER (cpu, \
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"Internal SIM error: invalid element number: %d ",\
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ELEMENT); \
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sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
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sim_stopped, SIM_SIGBUS); \
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} \
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if (VAL != cpu->fr[REG].FIELD [ELEMENT]) \
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TRACE_REGISTER (cpu, \
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"VR[%2d]." #FIELD " [%d] changes from " PRINTER \
|
|
" to " PRINTER , REG, \
|
|
ELEMENT, cpu->fr[REG].FIELD [ELEMENT], VAL); \
|
|
\
|
|
cpu->fr[REG].FIELD [ELEMENT] = VAL; \
|
|
} \
|
|
while (0)
|
|
|
|
void
|
|
aarch64_set_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element, uint64_t val)
|
|
{
|
|
SET_VEC_ELEMENT (reg, element, val, v, "%16" PRIx64);
|
|
}
|
|
|
|
void
|
|
aarch64_set_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element, uint32_t val)
|
|
{
|
|
SET_VEC_ELEMENT (reg, element, val, w, "%8x");
|
|
}
|
|
|
|
void
|
|
aarch64_set_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element, uint16_t val)
|
|
{
|
|
SET_VEC_ELEMENT (reg, element, val, h, "%4x");
|
|
}
|
|
|
|
void
|
|
aarch64_set_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element, uint8_t val)
|
|
{
|
|
SET_VEC_ELEMENT (reg, element, val, b, "%x");
|
|
}
|
|
|
|
void
|
|
aarch64_set_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element, int64_t val)
|
|
{
|
|
SET_VEC_ELEMENT (reg, element, val, V, "%16" PRIx64);
|
|
}
|
|
|
|
void
|
|
aarch64_set_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element, int32_t val)
|
|
{
|
|
SET_VEC_ELEMENT (reg, element, val, W, "%8x");
|
|
}
|
|
|
|
void
|
|
aarch64_set_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element, int16_t val)
|
|
{
|
|
SET_VEC_ELEMENT (reg, element, val, H, "%4x");
|
|
}
|
|
|
|
void
|
|
aarch64_set_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element, int8_t val)
|
|
{
|
|
SET_VEC_ELEMENT (reg, element, val, B, "%x");
|
|
}
|
|
|
|
void
|
|
aarch64_set_vec_float (sim_cpu *cpu, VReg reg, unsigned element, float val)
|
|
{
|
|
SET_VEC_ELEMENT (reg, element, val, S, "%f");
|
|
}
|
|
|
|
void
|
|
aarch64_set_vec_double (sim_cpu *cpu, VReg reg, unsigned element, double val)
|
|
{
|
|
SET_VEC_ELEMENT (reg, element, val, D, "%f");
|
|
}
|
|
|
|
void
|
|
aarch64_set_FPSR (sim_cpu *cpu, uint32_t value)
|
|
{
|
|
if (cpu->FPSR != value)
|
|
TRACE_REGISTER (cpu,
|
|
"FPSR changes from %x to %x", cpu->FPSR, value);
|
|
|
|
cpu->FPSR = value & FPSR_ALL_FPSRS;
|
|
}
|
|
|
|
uint32_t
|
|
aarch64_get_FPSR (sim_cpu *cpu)
|
|
{
|
|
return cpu->FPSR;
|
|
}
|
|
|
|
void
|
|
aarch64_set_FPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value)
|
|
{
|
|
uint32_t old_FPSR = cpu->FPSR;
|
|
|
|
mask &= FPSR_ALL_FPSRS;
|
|
cpu->FPSR &= ~mask;
|
|
cpu->FPSR |= (value & mask);
|
|
|
|
if (cpu->FPSR != old_FPSR)
|
|
TRACE_REGISTER (cpu,
|
|
"FPSR changes from %x to %x", old_FPSR, cpu->FPSR);
|
|
}
|
|
|
|
uint32_t
|
|
aarch64_get_FPSR_bits (sim_cpu *cpu, uint32_t mask)
|
|
{
|
|
mask &= FPSR_ALL_FPSRS;
|
|
return cpu->FPSR & mask;
|
|
}
|
|
|
|
int
|
|
aarch64_test_FPSR_bit (sim_cpu *cpu, FPSRMask flag)
|
|
{
|
|
return cpu->FPSR & flag;
|
|
}
|
|
|
|
uint64_t
|
|
aarch64_get_thread_id (sim_cpu *cpu)
|
|
{
|
|
return cpu->tpidr;
|
|
}
|
|
|
|
uint32_t
|
|
aarch64_get_FPCR (sim_cpu *cpu)
|
|
{
|
|
return cpu->FPCR;
|
|
}
|
|
|
|
void
|
|
aarch64_set_FPCR (sim_cpu *cpu, uint32_t val)
|
|
{
|
|
if (cpu->FPCR != val)
|
|
TRACE_REGISTER (cpu,
|
|
"FPCR changes from %x to %x", cpu->FPCR, val);
|
|
cpu->FPCR = val;
|
|
}
|