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* doc/c-i860.texi: New file.
* doc/Makefile.am (CPU_DOCS): Add c-i860.texi.
* doc/Makefile.in: Regenerate.
* doc/all.texi: Add I860 as relevant architecture.
* doc/as.texinfo: Include i860 dependent file c-i860.texi.
91 lines
2.5 KiB
Plaintext
91 lines
2.5 KiB
Plaintext
@c Copyright (C) 2000 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node i860-Dependent
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@chapter Intel i860 Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter Intel i860 Dependent Features
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@end ifclear
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@ignore
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@c FIXME: This is basically a stub for i860. There is tons more information
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that I will add later (jle@cygnus.com). The assembler is still being
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written. The i860 assembler that existed previously was never finished
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and doesn't even build. Further, its not BFD_ASSEMBLER and it doesn't
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do ELF (it doesn't do anything, but you get the point).
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@end ignore
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@cindex i860 support
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@menu
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* Options-i860:: i860 Command-line Options
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* Directives-i860:: i860 Machine Directives
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* Opcodes for i860:: i860 Opcodes
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@end menu
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@node Options-i860
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@section i860 Command-line Options
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@subsection SVR4 compatibility options
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@table @code
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@item -V
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Print assembler version.
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@item -Qy
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Ignored.
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@item -Qn
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Ignored.
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@end table
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@subsection Other options
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@table @code
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@item -EL
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Select little endian output (this is the default).
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@item -EB
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Select big endian output. Note that the i860 always reads instructions
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as little endian data, so this option only effects data and not
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instructions.
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@end table
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@node Directives-i860
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@section i860 Machine Directives
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@cindex machine directives, i860
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@cindex i860 machine directives
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@table @code
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@cindex @code{dual} directive, i860
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@item .dual
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Enter dual instruction mode. While this directive is supported, the
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preferred way to use dual instruction mode is to explicitly code
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the dual bit with the @code{d.} prefix.
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@end table
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@table @code
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@cindex @code{enddual} directive, i860
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@item .enddual
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Exit dual instruction mode. While this directive is supported, the
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preferred way to use dual instruction mode is to explicitly code
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the dual bit with the @code{d.} prefix.
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@end table
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@table @code
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@cindex @code{atmp} directive, i860
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@item .atmp
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Change the temporary register used when expanding pseudo operations. The
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default register is @code{r31}.
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@end table
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@node Opcodes for i860
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@section i860 Opcodes
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@cindex opcodes, i860
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@cindex i860 opcodes
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All of the Intel i860 machine instructions are supported.
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Some opcodes are processed beyond simply emitting a single corresponding
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instruction. For example, @samp{mov} and other instructions with larg
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displacements may be expanded into 2 or 3 instructions (FIXME: add details).
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