binutils-gdb/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
Nelson Chu aed44286ef RISC-V: Updated the default ISA spec to 20191213.
Update the default ISA spec from 2.2 to 20191213 will change the default
version of i from 2.0 to 2.1.  Since zicsr and zifencei are separated
from i 2.1, users need to add them in the architecture string if they need
fence.i and csr instructions.  Besides, we also allow old ISA spec can
recognize zicsr and zifencei, but we won't output them since they are
already included in the i extension when i's version is less than 2.1.

bfd/
	* elfxx-riscv.c (riscv_parse_add_subset): Allow old ISA spec can
	recognize zicsr and zifencei.
gas/
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Updated to 20191213.
	* testsuite/gas/riscv/csr-version-1p10.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/option-arch-03.d: Updated i's version to 2.1.
	* testsuite/gas/riscv/option-arch-03.s: Likewise.
ld/
	* testsuite/ld-riscv-elf/call-relax.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated i's version to 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-01b.: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Added zifencei
	into Tag_RISCV_arch since it is added implied when i's version is
	larger than 2.1.
2022-01-07 18:48:29 +08:00

2 lines
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ArmAsm

.attribute arch, "rv32i2p1_m2p0"