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979 lines
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979 lines
37 KiB
Plaintext
@c Copyright (C) 2009-2024 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node S/390-Dependent
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@chapter IBM S/390 Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter IBM S/390 Dependent Features
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@end ifclear
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@cindex s390 support
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The s390 version of @code{@value{AS}} supports two architectures modes
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and eleven chip levels. The architecture modes are the Enterprise System
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Architecture (ESA) and the newer z/Architecture mode. The chip levels
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are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec
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(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13
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(or arch11), z14 (or arch12), z15 (or arch13), or z16 (or arch14).
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@menu
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* s390 Options:: Command-line Options.
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* s390 Characters:: Special Characters.
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* s390 Syntax:: Assembler Instruction syntax.
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* s390 Directives:: Assembler Directives.
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* s390 Floating Point:: Floating Point.
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@end menu
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@node s390 Options
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@section Options
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@cindex options for s390
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@cindex s390 options
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The following table lists all available s390 specific options:
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@table @code
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@cindex @samp{-m31} option, s390
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@cindex @samp{-m64} option, s390
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@item -m31 | -m64
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Select 31- or 64-bit ABI implying a word size of 32- or 64-bit.
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These options are only available with the ELF object file format, and
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require that the necessary BFD support has been included (on a 31-bit
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platform you must add --enable-64-bit-bfd on the call to the configure
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script to enable 64-bit usage and use s390x as target platform).
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@cindex @samp{-mesa} option, s390
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@cindex @samp{-mzarch} option, s390
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@item -mesa | -mzarch
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Select the architecture mode, either the Enterprise System Architecture
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(esa) mode or the z/Architecture mode (zarch).
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The 64-bit instructions are only available with the z/Architecture mode.
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The combination of @samp{-m64} and @samp{-mesa} results in a warning
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message.
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@cindex @samp{-march=} option, s390
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@item -march=@var{CPU}
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This option specifies the target processor. The following processor names
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are recognized:
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@code{g5} (or @code{arch3}),
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@code{g6},
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@code{z900} (or @code{arch5}),
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@code{z990} (or @code{arch6}),
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@code{z9-109},
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@code{z9-ec} (or @code{arch7}),
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@code{z10} (or @code{arch8}),
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@code{z196} (or @code{arch9}),
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@code{zEC12} (or @code{arch10}),
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@code{z13} (or @code{arch11}),
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@code{z14} (or @code{arch12}),
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@code{z15} (or @code{arch13}), and
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@code{z16} (or @code{arch14}).
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Assembling an instruction that is not supported on the target
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processor results in an error message.
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The processor names starting with @code{arch} refer to the edition
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number in the Principle of Operations manual. They can be used as
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alternate processor names and have been added for compatibility with
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the IBM XL compiler.
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@code{arch3}, @code{g5} and @code{g6} cannot be used with the
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@samp{-mzarch} option since the z/Architecture mode is not supported
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on these processor levels.
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There is no @code{arch4} option supported. @code{arch4} matches
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@code{-march=arch5 -mesa}.
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@cindex @samp{-mregnames} option, s390
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@item -mregnames
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Allow symbolic names for registers.
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@cindex @samp{-mno-regnames} option, s390
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@item -mno-regnames
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Do not allow symbolic names for registers.
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@cindex @samp{-mwarn-areg-zero} option, s390
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@item -mwarn-areg-zero
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Warn whenever the operand for a base or index register has been specified
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but evaluates to zero. This can indicate the misuse of general purpose
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register 0 as an address register.
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@end table
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@node s390 Characters
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@section Special Characters
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@cindex line comment character, s390
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@cindex s390 line comment character
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@samp{#} is the line comment character.
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If a @samp{#} appears as the first character of a line then the whole
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line is treated as a comment, but in this case the line could also be
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a logical line number directive (@pxref{Comments}) or a preprocessor
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control command (@pxref{Preprocessing}).
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@cindex line separator, s390
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@cindex statement separator, s390
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@cindex s390 line separator
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The @samp{;} character can be used instead of a newline to separate
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statements.
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@node s390 Syntax
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@section Instruction syntax
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@cindex instruction syntax, s390
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@cindex s390 instruction syntax
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The assembler syntax closely follows the syntax outlined in
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Enterprise Systems Architecture/390 Principles of Operation (SA22-7201)
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and the z/Architecture Principles of Operation (SA22-7832).
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Each instruction has two major parts, the instruction mnemonic
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and the instruction operands. The instruction format varies.
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@menu
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* s390 Register:: Register Naming
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* s390 Mnemonics:: Instruction Mnemonics
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* s390 Operands:: Instruction Operands
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* s390 Formats:: Instruction Formats
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* s390 Aliases:: Instruction Aliases
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* s390 Operand Modifier:: Instruction Operand Modifier
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* s390 Instruction Marker:: Instruction Marker
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* s390 Literal Pool Entries:: Literal Pool Entries
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@end menu
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@node s390 Register
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@subsection Register naming
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@cindex register naming, s390
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@cindex s390 register naming
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The @code{@value{AS}} recognizes a number of predefined symbols for the
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various processor registers. A register specification in one of the
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instruction formats is an unsigned integer between 0 and 15. The specific
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instruction and the position of the register in the instruction format
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denotes the type of the register. The register symbols are prefixed with
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@samp{%}:
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@display
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@multitable {%rN} {the 16 general purpose registers, 0 <= N <= 15}
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@item %rN @tab the 16 general purpose registers, 0 <= N <= 15
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@item %fN @tab the 16 floating point registers, 0 <= N <= 15
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@item %aN @tab the 16 access registers, 0 <= N <= 15
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@item %cN @tab the 16 control registers, 0 <= N <= 15
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@item %lit @tab an alias for the general purpose register %r13
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@item %sp @tab an alias for the general purpose register %r15
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@end multitable
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@end display
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@node s390 Mnemonics
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@subsection Instruction Mnemonics
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@cindex instruction mnemonics, s390
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@cindex s390 instruction mnemonics
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All instructions documented in the Principles of Operation are supported
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with the mnemonic and order of operands as described.
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The instruction mnemonic identifies the instruction format
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(@ref{s390 Formats}) and the specific operation code for the instruction.
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For example, the @samp{lr} mnemonic denotes the instruction format @samp{RR}
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with the operation code @samp{0x18}.
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The definition of the various mnemonics follows a scheme, where the first
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character usually hint at the type of the instruction:
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@display
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@multitable {sla, sll} {if r is the last character the instruction operates on registers}
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@item a @tab add instruction, for example @samp{al} for add logical 32-bit
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@item b @tab branch instruction, for example @samp{bc} for branch on condition
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@item c @tab compare or convert instruction, for example @samp{cr} for compare
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register 32-bit
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@item d @tab divide instruction, for example @samp{dlr} divide logical register
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64-bit to 32-bit
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@item i @tab insert instruction, for example @samp{ic} insert character
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@item l @tab load instruction, for example @samp{ltr} load and test register
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@item mv @tab move instruction, for example @samp{mvc} move character
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@item m @tab multiply instruction, for example @samp{mh} multiply halfword
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@item n @tab and instruction, for example @samp{ni} and immediate
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@item o @tab or instruction, for example @samp{oc} or character
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@item sla, sll @tab shift left single instruction
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@item sra, srl @tab shift right single instruction
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@item st @tab store instruction, for example @samp{stm} store multiple
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@item s @tab subtract instruction, for example @samp{slr} subtract
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logical 32-bit
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@item t @tab test or translate instruction, of example @samp{tm} test under mask
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@item x @tab exclusive or instruction, for example @samp{xc} exclusive or
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character
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@end multitable
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@end display
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Certain characters at the end of the mnemonic may describe a property
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of the instruction:
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@display
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@multitable {c} {if r is the last character the instruction operates on registers}
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@item c @tab the instruction uses a 8-bit character operand
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@item f @tab the instruction extends a 32-bit operand to 64 bit
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@item g @tab the operands are treated as 64-bit values
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@item h @tab the operand uses a 16-bit halfword operand
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@item i @tab the instruction uses an immediate operand
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@item l @tab the instruction uses unsigned, logical operands
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@item m @tab the instruction uses a mask or operates on multiple values
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@item r @tab if r is the last character, the instruction operates on registers
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@item y @tab the instruction uses 20-bit displacements
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@end multitable
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@end display
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There are many exceptions to the scheme outlined in the above lists, in
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particular for the privileged instructions. For non-privileged
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instruction it works quite well, for example the instruction @samp{clgfr}
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c: compare instruction, l: unsigned operands, g: 64-bit operands,
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f: 32- to 64-bit extension, r: register operands. The instruction compares
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an 64-bit value in a register with the zero extended 32-bit value from
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a second register.
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For a complete list of all mnemonics see appendix B in the Principles
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of Operation.
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@node s390 Operands
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@subsection Instruction Operands
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@cindex instruction operands, s390
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@cindex s390 instruction operands
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Instruction operands can be grouped into three classes, operands located
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in registers, immediate operands, and operands in storage.
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A register operand can be located in general, floating-point, access,
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or control register. The register is identified by a four-bit field.
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The field containing the register operand is called the R field.
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Immediate operands are contained within the instruction and can have
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8, 16 or 32 bits. The field containing the immediate operand is called
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the I field. Dependent on the instruction the I field is either signed
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or unsigned.
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A storage operand consists of an address and a length. The address of a
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storage operands can be specified in any of these ways:
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@itemize
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@item The content of a single general R
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@item The sum of the content of a general register called the base
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register B plus the content of a displacement field D
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@item The sum of the contents of two general registers called the
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index register X and the base register B plus the content of a
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displacement field
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@item The sum of the current instruction address and a 32-bit signed
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immediate field multiplied by two.
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@end itemize
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The length of a storage operand can be:
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@itemize
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@item Implied by the instruction
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@item Specified by a bitmask
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@item Specified by a four-bit or eight-bit length field L
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@item Specified by the content of a general register
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@end itemize
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The notation for storage operand addresses formed from multiple fields is
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as follows:
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@table @code
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@item Dn(Bn)
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the address for operand number n is formed from the content of general
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register Bn called the base register and the displacement field Dn.
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@item Dn(Xn,Bn)
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the address for operand number n is formed from the content of general
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register Xn called the index register, general register Bn called the
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base register and the displacement field Dn.
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@item Dn(Ln,Bn)
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the address for operand number n is formed from the content of general
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register Bn called the base register and the displacement field Dn.
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The length of the operand n is specified by the field Ln.
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@end table
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The base registers Bn and the index registers Xn of a storage operand can
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be skipped. If Bn and Xn are skipped, a zero will be stored to the operand
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field. The notation changes as follows:
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@display
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@multitable @columnfractions 0.30 0.30
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@headitem full notation @tab short notation
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@item Dn(0,Bn) @tab Dn(Bn)
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@item Dn(0,0) @tab Dn
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@item Dn(0) @tab Dn
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@item Dn(Ln,0) @tab Dn(Ln)
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@end multitable
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@end display
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@node s390 Formats
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@subsection Instruction Formats
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@cindex instruction formats, s390
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@cindex s390 instruction formats
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The Principles of Operation manuals lists 35 instruction formats where
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some of the formats have multiple variants. For the @samp{.insn}
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pseudo directive the assembler recognizes some of the formats.
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Typically, the most general variant of the instruction format is used
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by the @samp{.insn} directive.
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The following table lists the abbreviations used in the table of
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instruction formats:
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@display
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@multitable {OpCode / OpCd} {Displacement lower 12 bits for operand x.}
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@item OpCode / OpCd @tab Part of the op code.
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@item Bx @tab Base register number for operand x.
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@item Dx @tab Displacement for operand x.
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@item DLx @tab Displacement lower 12 bits for operand x.
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@item DHx @tab Displacement higher 8-bits for operand x.
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@item Rx @tab Register number for operand x.
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@item Xx @tab Index register number for operand x.
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@item Ix @tab Signed immediate for operand x.
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@item Ux @tab Unsigned immediate for operand x.
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@end multitable
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@end display
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An instruction is two, four, or six bytes in length and must be aligned
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on a 2 byte boundary. The first two bits of the instruction specify the
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length of the instruction, 00 indicates a two byte instruction, 01 and 10
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indicates a four byte instruction, and 11 indicates a six byte instruction.
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The following table lists the s390 instruction formats that are available
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with the @samp{.insn} pseudo directive:
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@table @code
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@item E format
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@verbatim
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+-------------+
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| OpCode |
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+-------------+
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0 15
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@end verbatim
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@item RI format: <insn> R1,I2
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@verbatim
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+--------+----+----+------------------+
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| OpCode | R1 |OpCd| I2 |
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+--------+----+----+------------------+
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0 8 12 16 31
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@end verbatim
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@item RIE format: <insn> R1,R3,I2
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@verbatim
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+--------+----+----+------------------+--------+--------+
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| OpCode | R1 | R3 | I2 |////////| OpCode |
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+--------+----+----+------------------+--------+--------+
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0 8 12 16 32 40 47
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@end verbatim
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@item RIL format: <insn> R1,I2
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@verbatim
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+--------+----+----+------------------------------------+
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| OpCode | R1 |OpCd| I2 |
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+--------+----+----+------------------------------------+
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0 8 12 16 47
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@end verbatim
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@item RILU format: <insn> R1,U2
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@verbatim
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+--------+----+----+------------------------------------+
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| OpCode | R1 |OpCd| U2 |
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+--------+----+----+------------------------------------+
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0 8 12 16 47
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@end verbatim
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@item RIS format: <insn> R1,I2,M3,D4(B4)
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@verbatim
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+--------+----+----+----+-------------+--------+--------+
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| OpCode | R1 | M3 | B4 | D4 | I2 | Opcode |
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+--------+----+----+----+-------------+--------+--------+
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0 8 12 16 20 32 36 47
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@end verbatim
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@item RR format: <insn> R1,R2
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@verbatim
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+--------+----+----+
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| OpCode | R1 | R2 |
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+--------+----+----+
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0 8 12 15
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@end verbatim
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@item RRE format: <insn> R1,R2
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@verbatim
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+------------------+--------+----+----+
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| OpCode |////////| R1 | R2 |
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+------------------+--------+----+----+
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0 16 24 28 31
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@end verbatim
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@item RRF format: <insn> R1,R2,R3,M4
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@verbatim
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+------------------+----+----+----+----+
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| OpCode | R3 | M4 | R1 | R2 |
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+------------------+----+----+----+----+
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0 16 20 24 28 31
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@end verbatim
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@item RRS format: <insn> R1,R2,M3,D4(B4)
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@verbatim
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+--------+----+----+----+-------------+----+----+--------+
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| OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode |
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+--------+----+----+----+-------------+----+----+--------+
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0 8 12 16 20 32 36 40 47
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@end verbatim
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@item RS format: <insn> R1,R3,D2(B2)
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@verbatim
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+--------+----+----+----+-------------+
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| OpCode | R1 | R3 | B2 | D2 |
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+--------+----+----+----+-------------+
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0 8 12 16 20 31
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@end verbatim
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@item RSE format: <insn> R1,R3,D2(B2)
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@verbatim
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+--------+----+----+----+-------------+--------+--------+
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| OpCode | R1 | R3 | B2 | D2 |////////| OpCode |
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+--------+----+----+----+-------------+--------+--------+
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0 8 12 16 20 32 40 47
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@end verbatim
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@item RSI format: <insn> R1,R3,I2
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@verbatim
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+--------+----+----+------------------------------------+
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| OpCode | R1 | R3 | I2 |
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+--------+----+----+------------------------------------+
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0 8 12 16 47
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@end verbatim
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@item RSY format: <insn> R1,R3,D2(B2)
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@verbatim
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+--------+----+----+----+-------------+--------+--------+
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| OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode |
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+--------+----+----+----+-------------+--------+--------+
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0 8 12 16 20 32 40 47
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@end verbatim
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@item RX format: <insn> R1,D2(X2,B2)
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@verbatim
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+--------+----+----+----+-------------+
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| OpCode | R1 | X2 | B2 | D2 |
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+--------+----+----+----+-------------+
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0 8 12 16 20 31
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@end verbatim
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@item RXE format: <insn> R1,D2(X2,B2)
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@verbatim
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+--------+----+----+----+-------------+--------+--------+
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| OpCode | R1 | X2 | B2 | D2 |////////| OpCode |
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+--------+----+----+----+-------------+--------+--------+
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0 8 12 16 20 32 40 47
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@end verbatim
|
|
|
|
@item RXF format: <insn> R1,R3,D2(X2,B2)
|
|
@verbatim
|
|
+--------+----+----+----+-------------+----+---+--------+
|
|
| OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode |
|
|
+--------+----+----+----+-------------+----+---+--------+
|
|
0 8 12 16 20 32 36 40 47
|
|
@end verbatim
|
|
|
|
@item RXY format: <insn> R1,D2(X2,B2)
|
|
@verbatim
|
|
+--------+----+----+----+-------------+--------+--------+
|
|
| OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode |
|
|
+--------+----+----+----+-------------+--------+--------+
|
|
0 8 12 16 20 32 36 40 47
|
|
@end verbatim
|
|
|
|
@item S format: <insn> D2(B2)
|
|
@verbatim
|
|
+------------------+----+-------------+
|
|
| OpCode | B2 | D2 |
|
|
+------------------+----+-------------+
|
|
0 16 20 31
|
|
@end verbatim
|
|
|
|
@item SI format: <insn> D1(B1),I2
|
|
@verbatim
|
|
+--------+---------+----+-------------+
|
|
| OpCode | I2 | B1 | D1 |
|
|
+--------+---------+----+-------------+
|
|
0 8 16 20 31
|
|
@end verbatim
|
|
|
|
@item SIY format: <insn> D1(B1),U2
|
|
@verbatim
|
|
+--------+---------+----+-------------+--------+--------+
|
|
| OpCode | I2 | B1 | DL1 | DH1 | OpCode |
|
|
+--------+---------+----+-------------+--------+--------+
|
|
0 8 16 20 32 36 40 47
|
|
@end verbatim
|
|
|
|
@item SIL format: <insn> D1(B1),I2
|
|
@verbatim
|
|
+------------------+----+-------------+-----------------+
|
|
| OpCode | B1 | D1 | I2 |
|
|
+------------------+----+-------------+-----------------+
|
|
0 16 20 32 47
|
|
@end verbatim
|
|
|
|
@item SS format: <insn> D1(R1,B1),D2(B3),R3
|
|
@verbatim
|
|
+--------+----+----+----+-------------+----+------------+
|
|
| OpCode | R1 | R3 | B1 | D1 | B2 | D2 |
|
|
+--------+----+----+----+-------------+----+------------+
|
|
0 8 12 16 20 32 36 47
|
|
@end verbatim
|
|
|
|
@item SSE format: <insn> D1(B1),D2(B2)
|
|
@verbatim
|
|
+------------------+----+-------------+----+------------+
|
|
| OpCode | B1 | D1 | B2 | D2 |
|
|
+------------------+----+-------------+----+------------+
|
|
0 8 12 16 20 32 36 47
|
|
@end verbatim
|
|
|
|
@item SSF format: <insn> D1(B1),D2(B2),R3
|
|
@verbatim
|
|
+--------+----+----+----+-------------+----+------------+
|
|
| OpCode | R3 |OpCd| B1 | D1 | B2 | D2 |
|
|
+--------+----+----+----+-------------+----+------------+
|
|
0 8 12 16 20 32 36 47
|
|
@end verbatim
|
|
|
|
@item VRV format: <insn> V1,D2(V2,B2),M3
|
|
@verbatim
|
|
+--------+----+----+----+-------------+----+------------+
|
|
| OpCode | V1 | V2 | B2 | D2 | M3 | Opcode |
|
|
+--------+----+----+----+-------------+----+------------+
|
|
0 8 12 16 20 32 36 47
|
|
@end verbatim
|
|
|
|
@item VRI format: <insn> V1,V2,I3,M4,M5
|
|
@verbatim
|
|
+--------+----+----+-------------+----+----+------------+
|
|
| OpCode | V1 | V2 | I3 | M5 | M4 | Opcode |
|
|
+--------+----+----+-------------+----+----+------------+
|
|
0 8 12 16 28 32 36 47
|
|
@end verbatim
|
|
|
|
@item VRX format: <insn> V1,D2(R2,B2),M3
|
|
@verbatim
|
|
+--------+----+----+----+-------------+----+------------+
|
|
| OpCode | V1 | R2 | B2 | D2 | M3 | Opcode |
|
|
+--------+----+----+----+-------------+----+------------+
|
|
0 8 12 16 20 32 36 47
|
|
@end verbatim
|
|
|
|
@item VRS format: <insn> R1,V3,D2(B2),M4
|
|
@verbatim
|
|
+--------+----+----+----+-------------+----+------------+
|
|
| OpCode | R1 | V3 | B2 | D2 | M4 | Opcode |
|
|
+--------+----+----+----+-------------+----+------------+
|
|
0 8 12 16 20 32 36 47
|
|
@end verbatim
|
|
|
|
@item VRR format: <insn> V1,V2,V3,M4,M5,M6
|
|
@verbatim
|
|
+--------+----+----+----+---+----+----+----+------------+
|
|
| OpCode | V1 | V2 | V3 |///| M6 | M5 | M4 | Opcode |
|
|
+--------+----+----+----+---+----+----+----+------------+
|
|
0 8 12 16 24 28 32 36 47
|
|
@end verbatim
|
|
|
|
@item VSI format: <insn> V1,D2(B2),I3
|
|
@verbatim
|
|
+--------+---------+----+-------------+----+------------+
|
|
| OpCode | I3 | B2 | D2 | V1 | Opcode |
|
|
+--------+---------+----+-------------+----+------------+
|
|
0 8 16 20 32 36 47
|
|
@end verbatim
|
|
|
|
@end table
|
|
|
|
For the complete list of all instruction format variants see the
|
|
Principles of Operation manuals.
|
|
|
|
@node s390 Aliases
|
|
@subsection Instruction Aliases
|
|
@cindex instruction aliases, s390
|
|
@cindex s390 instruction aliases
|
|
|
|
A specific bit pattern can have multiple mnemonics, for example
|
|
the bit pattern @samp{0xa7000000} has the mnemonics @samp{tmh} and
|
|
@samp{tmlh}. In addition, there are a number of mnemonics recognized by
|
|
@code{@value{AS}} that are not present in the Principles of Operation.
|
|
These are the short forms of the branch instructions, where the condition
|
|
code mask operand is encoded in the mnemonic. This is relevant for the
|
|
branch instructions, the compare and branch instructions, and the
|
|
compare and trap instructions.
|
|
|
|
For the branch instructions there are 20 condition code strings that can
|
|
be used as part of the mnemonic in place of a mask operand in the instruction
|
|
format:
|
|
|
|
@display
|
|
@multitable @columnfractions .30 .30
|
|
@headitem instruction @tab short form
|
|
@item bcr M1,R2 @tab b<m>r R2
|
|
@item bc M1,D2(X2,B2) @tab b<m> D2(X2,B2)
|
|
@item brc M1,I2 @tab j<m> I2
|
|
@item brcl M1,I2 @tab jg<m> I2
|
|
@end multitable
|
|
@end display
|
|
|
|
In the mnemonic for a branch instruction the condition code string <m>
|
|
can be any of the following:
|
|
|
|
@display
|
|
@multitable {nle} {jump on not zero / if not zeros}
|
|
@item o @tab jump on overflow / if ones
|
|
@item h @tab jump on A high
|
|
@item p @tab jump on plus
|
|
@item nle @tab jump on not low or equal
|
|
@item l @tab jump on A low
|
|
@item m @tab jump on minus
|
|
@item nhe @tab jump on not high or equal
|
|
@item lh @tab jump on low or high
|
|
@item ne @tab jump on A not equal B
|
|
@item nz @tab jump on not zero / if not zeros
|
|
@item e @tab jump on A equal B
|
|
@item z @tab jump on zero / if zeroes
|
|
@item nlh @tab jump on not low or high
|
|
@item he @tab jump on high or equal
|
|
@item nl @tab jump on A not low
|
|
@item nm @tab jump on not minus / if not mixed
|
|
@item le @tab jump on low or equal
|
|
@item nh @tab jump on A not high
|
|
@item np @tab jump on not plus
|
|
@item no @tab jump on not overflow / if not ones
|
|
@end multitable
|
|
@end display
|
|
|
|
For the compare and branch, and compare and trap instructions there
|
|
are 12 condition code strings that can be used as part of the mnemonic in
|
|
place of a mask operand in the instruction format:
|
|
|
|
@display
|
|
@multitable @columnfractions .40 .40
|
|
@headitem instruction @tab short form
|
|
@item crb R1,R2,M3,D4(B4) @tab crb<m> R1,R2,D4(B4)
|
|
@item cgrb R1,R2,M3,D4(B4) @tab cgrb<m> R1,R2,D4(B4)
|
|
@item crj R1,R2,M3,I4 @tab crj<m> R1,R2,I4
|
|
@item cgrj R1,R2,M3,I4 @tab cgrj<m> R1,R2,I4
|
|
@item cib R1,I2,M3,D4(B4) @tab cib<m> R1,I2,D4(B4)
|
|
@item cgib R1,I2,M3,D4(B4) @tab cgib<m> R1,I2,D4(B4)
|
|
@item cij R1,I2,M3,I4 @tab cij<m> R1,I2,I4
|
|
@item cgij R1,I2,M3,I4 @tab cgij<m> R1,I2,I4
|
|
@item crt R1,R2,M3 @tab crt<m> R1,R2
|
|
@item cgrt R1,R2,M3 @tab cgrt<m> R1,R2
|
|
@item cit R1,I2,M3 @tab cit<m> R1,I2
|
|
@item cgit R1,I2,M3 @tab cgit<m> R1,I2
|
|
@item clrb R1,R2,M3,D4(B4) @tab clrb<m> R1,R2,D4(B4)
|
|
@item clgrb R1,R2,M3,D4(B4) @tab clgrb<m> R1,R2,D4(B4)
|
|
@item clrj R1,R2,M3,I4 @tab clrj<m> R1,R2,I4
|
|
@item clgrj R1,R2,M3,I4 @tab clgrj<m> R1,R2,I4
|
|
@item clib R1,I2,M3,D4(B4) @tab clib<m> R1,I2,D4(B4)
|
|
@item clgib R1,I2,M3,D4(B4) @tab clgib<m> R1,I2,D4(B4)
|
|
@item clij R1,I2,M3,I4 @tab clij<m> R1,I2,I4
|
|
@item clgij R1,I2,M3,I4 @tab clgij<m> R1,I2,I4
|
|
@item clrt R1,R2,M3 @tab clrt<m> R1,R2
|
|
@item clgrt R1,R2,M3 @tab clgrt<m> R1,R2
|
|
@item clfit R1,I2,M3 @tab clfit<m> R1,I2
|
|
@item clgit R1,I2,M3 @tab clgit<m> R1,I2
|
|
@end multitable
|
|
@end display
|
|
|
|
In the mnemonic for a compare and branch and compare and trap instruction
|
|
the condition code string <m> can be any of the following:
|
|
|
|
@display
|
|
@multitable {nle} {jump on not zero / if not zeros}
|
|
@item h @tab jump on A high
|
|
@item nle @tab jump on not low or equal
|
|
@item l @tab jump on A low
|
|
@item nhe @tab jump on not high or equal
|
|
@item ne @tab jump on A not equal B
|
|
@item lh @tab jump on low or high
|
|
@item e @tab jump on A equal B
|
|
@item nlh @tab jump on not low or high
|
|
@item nl @tab jump on A not low
|
|
@item he @tab jump on high or equal
|
|
@item nh @tab jump on A not high
|
|
@item le @tab jump on low or equal
|
|
@end multitable
|
|
@end display
|
|
|
|
@node s390 Operand Modifier
|
|
@subsection Instruction Operand Modifier
|
|
@cindex instruction operand modifier, s390
|
|
@cindex s390 instruction operand modifier
|
|
|
|
If a symbol modifier is attached to a symbol in an expression for an
|
|
instruction operand field, the symbol term is replaced with a reference
|
|
to an object in the global offset table (GOT) or the procedure linkage
|
|
table (PLT). The following expressions are allowed:
|
|
@samp{symbol@@modifier + constant},
|
|
@samp{symbol@@modifier + label + constant}, and
|
|
@samp{symbol@@modifier - label + constant}.
|
|
The term @samp{symbol} is the symbol that will be entered into the GOT or
|
|
PLT, @samp{label} is a local label, and @samp{constant} is an arbitrary
|
|
expression that the assembler can evaluate to a constant value.
|
|
|
|
The term @samp{(symbol + constant1)@@modifier +/- label + constant2}
|
|
is also accepted but a warning message is printed and the term is
|
|
converted to @samp{symbol@@modifier +/- label + constant1 + constant2}.
|
|
|
|
@table @code
|
|
@item @@got
|
|
@itemx @@got12
|
|
The @@got modifier can be used for displacement fields, 16-bit immediate
|
|
fields and 32-bit pc-relative immediate fields. The @@got12 modifier is
|
|
synonym to @@got. The symbol is added to the GOT. For displacement
|
|
fields and 16-bit immediate fields the symbol term is replaced with
|
|
the offset from the start of the GOT to the GOT slot for the symbol.
|
|
For a 32-bit pc-relative field the pc-relative offset to the GOT
|
|
slot from the current instruction address is used.
|
|
@item @@gotent
|
|
The @@gotent modifier can be used for 32-bit pc-relative immediate fields.
|
|
The symbol is added to the GOT and the symbol term is replaced with
|
|
the pc-relative offset from the current instruction to the GOT slot for the
|
|
symbol.
|
|
@item @@gotoff
|
|
The @@gotoff modifier can be used for 16-bit immediate fields. The symbol
|
|
term is replaced with the offset from the start of the GOT to the
|
|
address of the symbol.
|
|
@item @@gotplt
|
|
The @@gotplt modifier can be used for displacement fields, 16-bit immediate
|
|
fields, and 32-bit pc-relative immediate fields. A procedure linkage
|
|
table entry is generated for the symbol and a jump slot for the symbol
|
|
is added to the GOT. For displacement fields and 16-bit immediate
|
|
fields the symbol term is replaced with the offset from the start of the
|
|
GOT to the jump slot for the symbol. For a 32-bit pc-relative field
|
|
the pc-relative offset to the jump slot from the current instruction
|
|
address is used.
|
|
@item @@plt
|
|
The @@plt modifier can be used for 16-bit and 32-bit pc-relative immediate
|
|
fields. A procedure linkage table entry is generated for the symbol.
|
|
The symbol term is replaced with the relative offset from the current
|
|
instruction to the PLT entry for the symbol.
|
|
@item @@pltoff
|
|
The @@pltoff modifier can be used for 16-bit immediate fields. The symbol
|
|
term is replaced with the offset from the start of the PLT to the address
|
|
of the symbol.
|
|
@item @@gotntpoff
|
|
The @@gotntpoff modifier can be used for displacement fields. The symbol
|
|
is added to the static TLS block and the negated offset to the symbol
|
|
in the static TLS block is added to the GOT. The symbol term is replaced
|
|
with the offset to the GOT slot from the start of the GOT.
|
|
@item @@indntpoff
|
|
The @@indntpoff modifier can be used for 32-bit pc-relative immediate
|
|
fields. The symbol is added to the static TLS block and the negated offset
|
|
to the symbol in the static TLS block is added to the GOT. The symbol term
|
|
is replaced with the pc-relative offset to the GOT slot from the current
|
|
instruction address.
|
|
@end table
|
|
|
|
For more information about the thread local storage modifiers
|
|
@samp{gotntpoff} and @samp{indntpoff} see the ELF extension documentation
|
|
@samp{ELF Handling For Thread-Local Storage}.
|
|
|
|
@node s390 Instruction Marker
|
|
@subsection Instruction Marker
|
|
@cindex instruction marker, s390
|
|
@cindex s390 instruction marker
|
|
|
|
The thread local storage instruction markers are used by the linker to
|
|
perform code optimization.
|
|
|
|
@table @code
|
|
@item :tls_load
|
|
The :tls_load marker is used to flag the load instruction in the initial
|
|
exec TLS model that retrieves the offset from the thread pointer to a
|
|
thread local storage variable from the GOT.
|
|
@item :tls_gdcall
|
|
The :tls_gdcall marker is used to flag the branch-and-save instruction to
|
|
the __tls_get_offset function in the global dynamic TLS model.
|
|
@item :tls_ldcall
|
|
The :tls_ldcall marker is used to flag the branch-and-save instruction to
|
|
the __tls_get_offset function in the local dynamic TLS model.
|
|
@end table
|
|
|
|
For more information about the thread local storage instruction marker
|
|
and the linker optimizations see the ELF extension documentation
|
|
@samp{ELF Handling For Thread-Local Storage}.
|
|
|
|
@node s390 Literal Pool Entries
|
|
@subsection Literal Pool Entries
|
|
@cindex literal pool entries, s390
|
|
@cindex s390 literal pool entries
|
|
|
|
A literal pool is a collection of values. To access the values a pointer
|
|
to the literal pool is loaded to a register, the literal pool register.
|
|
Usually, register %r13 is used as the literal pool register
|
|
(@ref{s390 Register}). Literal pool entries are created by adding the
|
|
suffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an
|
|
instruction operand. The expression is added to the literal pool and the
|
|
operand is replaced with the offset to the literal in the literal pool.
|
|
|
|
@table @code
|
|
@item :lit1
|
|
The literal pool entry is created as an 8-bit value. An operand modifier
|
|
must not be used for the original expression.
|
|
@item :lit2
|
|
The literal pool entry is created as a 16 bit value. The operand modifier
|
|
@@got may be used in the original expression. The term @samp{x@@got:lit2}
|
|
will put the got offset for the global symbol x to the literal pool as
|
|
16 bit value.
|
|
@item :lit4
|
|
The literal pool entry is created as a 32-bit value. The operand modifier
|
|
@@got and @@plt may be used in the original expression. The term
|
|
@samp{x@@got:lit4} will put the got offset for the global symbol x to the
|
|
literal pool as a 32-bit value. The term @samp{x@@plt:lit4} will put the
|
|
plt offset for the global symbol x to the literal pool as a 32-bit value.
|
|
@item :lit8
|
|
The literal pool entry is created as a 64-bit value. The operand modifier
|
|
@@got and @@plt may be used in the original expression. The term
|
|
@samp{x@@got:lit8} will put the got offset for the global symbol x to the
|
|
literal pool as a 64-bit value. The term @samp{x@@plt:lit8} will put the
|
|
plt offset for the global symbol x to the literal pool as a 64-bit value.
|
|
@end table
|
|
|
|
The assembler directive @samp{.ltorg} is used to emit all literal pool
|
|
entries to the current position.
|
|
|
|
@node s390 Directives
|
|
@section Assembler Directives
|
|
|
|
@code{@value{AS}} for s390 supports all of the standard ELF
|
|
assembler directives as outlined in the main part of this document.
|
|
Some directives have been extended and there are some additional
|
|
directives, which are only available for the s390 @code{@value{AS}}.
|
|
|
|
@table @code
|
|
@cindex @code{.insn} directive, s390
|
|
@item .insn
|
|
This directive permits the numeric representation of an instructions
|
|
and makes the assembler insert the operands according to one of the
|
|
instructions formats for @samp{.insn} (@ref{s390 Formats}).
|
|
For example, the instruction @samp{l %r1,24(%r15)} could be written as
|
|
@samp{.insn rx,0x58000000,%r1,24(%r15)}.
|
|
@cindex @code{.short} directive, s390
|
|
@cindex @code{.long} directive, s390
|
|
@cindex @code{.quad} directive, s390
|
|
@item .short
|
|
@itemx .long
|
|
@itemx .quad
|
|
This directive places one or more 16-bit (.short), 32-bit (.long), or
|
|
64-bit (.quad) values into the current section. If an ELF or TLS modifier
|
|
is used only the following expressions are allowed:
|
|
@samp{symbol@@modifier + constant},
|
|
@samp{symbol@@modifier + label + constant}, and
|
|
@samp{symbol@@modifier - label + constant}.
|
|
The following modifiers are available:
|
|
@table @code
|
|
@item @@got
|
|
@itemx @@got12
|
|
The @@got modifier can be used for .short, .long and .quad. The @@got12
|
|
modifier is synonym to @@got. The symbol is added to the GOT. The symbol
|
|
term is replaced with offset from the start of the GOT to the GOT slot for
|
|
the symbol.
|
|
@item @@gotoff
|
|
The @@gotoff modifier can be used for .short, .long and .quad. The symbol
|
|
term is replaced with the offset from the start of the GOT to the address
|
|
of the symbol.
|
|
@item @@gotplt
|
|
The @@gotplt modifier can be used for .long and .quad. A procedure linkage
|
|
table entry is generated for the symbol and a jump slot for the symbol
|
|
is added to the GOT. The symbol term is replaced with the offset from the
|
|
start of the GOT to the jump slot for the symbol.
|
|
@item @@plt
|
|
The @@plt modifier can be used for .long and .quad. A procedure linkage
|
|
table entry us generated for the symbol. The symbol term is replaced with
|
|
the address of the PLT entry for the symbol.
|
|
@item @@pltoff
|
|
The @@pltoff modifier can be used for .short, .long and .quad. The symbol
|
|
term is replaced with the offset from the start of the PLT to the address
|
|
of the symbol.
|
|
@item @@tlsgd
|
|
@itemx @@tlsldm
|
|
The @@tlsgd and @@tlsldm modifier can be used for .long and .quad. A
|
|
tls_index structure for the symbol is added to the GOT. The symbol term is
|
|
replaced with the offset from the start of the GOT to the tls_index structure.
|
|
@item @@gotntpoff
|
|
@itemx @@indntpoff
|
|
The @@gotntpoff and @@indntpoff modifier can be used for .long and .quad.
|
|
The symbol is added to the static TLS block and the negated offset to the
|
|
symbol in the static TLS block is added to the GOT. For @@gotntpoff the
|
|
symbol term is replaced with the offset from the start of the GOT to the
|
|
GOT slot, for @@indntpoff the symbol term is replaced with the address
|
|
of the GOT slot.
|
|
@item @@dtpoff
|
|
The @@dtpoff modifier can be used for .long and .quad. The symbol term
|
|
is replaced with the offset of the symbol relative to the start of the
|
|
TLS block it is contained in.
|
|
@item @@ntpoff
|
|
The @@ntpoff modifier can be used for .long and .quad. The symbol term
|
|
is replaced with the offset of the symbol relative to the TCB pointer.
|
|
@end table
|
|
|
|
For more information about the thread local storage modifiers see the
|
|
ELF extension documentation @samp{ELF Handling For Thread-Local Storage}.
|
|
|
|
@cindex @code{.ltorg} directive, s390
|
|
@item .ltorg
|
|
This directive causes the current contents of the literal pool to be
|
|
dumped to the current location (@ref{s390 Literal Pool Entries}).
|
|
|
|
@cindex @code{.machine} directive, s390
|
|
@item .machine @var{STRING}[+@var{EXTENSION}]@dots{}
|
|
|
|
This directive allows changing the machine for which code is
|
|
generated. @code{string} may be any of the @code{-march=}
|
|
selection options, or @code{push}, or @code{pop}. @code{.machine
|
|
push} saves the currently selected cpu, which may be restored with
|
|
@code{.machine pop}. Be aware that the cpu string has to be put
|
|
into double quotes in case it contains characters not appropriate
|
|
for identifiers. So you have to write @code{"z9-109"} instead of
|
|
just @code{z9-109}. Extensions can be specified after the cpu
|
|
name, separated by plus characters. Valid extensions are:
|
|
@code{htm},
|
|
@code{nohtm},
|
|
@code{vx},
|
|
@code{novx}.
|
|
They extend the basic instruction set with features from a higher
|
|
cpu level, or remove support for a feature from the given cpu
|
|
level.
|
|
|
|
Example: @code{z13+nohtm} allows all instructions of the z13 cpu
|
|
except instructions from the HTM facility.
|
|
|
|
@cindex @code{.machinemode} directive, s390
|
|
@item .machinemode string
|
|
This directive allows one to change the architecture mode for which code
|
|
is being generated. @code{string} may be @code{esa}, @code{zarch},
|
|
@code{zarch_nohighgprs}, @code{push}, or @code{pop}.
|
|
@code{.machinemode zarch_nohighgprs} can be used to prevent the
|
|
@code{highgprs} flag from being set in the ELF header of the output
|
|
file. This is useful in situations where the code is gated with a
|
|
runtime check which makes sure that the code is only executed on
|
|
kernels providing the @code{highgprs} feature.
|
|
@code{.machinemode push} saves the currently selected mode, which may
|
|
be restored with @code{.machinemode pop}.
|
|
@end table
|
|
|
|
@node s390 Floating Point
|
|
@section Floating Point
|
|
@cindex floating point, s390
|
|
@cindex s390 floating point
|
|
|
|
The assembler recognizes both the @sc{ieee} floating-point instruction and
|
|
the hexadecimal floating-point instructions. The floating-point constructors
|
|
@samp{.float}, @samp{.single}, and @samp{.double} always emit the
|
|
@sc{ieee} format. To assemble hexadecimal floating-point constants the
|
|
@samp{.long} and @samp{.quad} directives must be used.
|