James Bowman 3b4b0a629a FT32: support for FT32B processor - part 1 ... FT32B is a new FT32 family member. It has a code compression scheme, which requires the use of linker relaxations. The change is quite large, so submission is in several parts. Part 1 adds a 15-bit instruction field, and CPU-specific functions for the code compression that are used in binutils and GDB. bfd/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-ft32.c: Add HOWTO R_FT32_15. * reloc.c: Add BFD_RELOC_FT32_15. gas/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * config/tc-ft32.c (md_assemble): Replace FT32_FLD_K8 with K15. (md_apply_fix, tc_gen_reloc): Add BFD_RELOC_FT32_15. include/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * elf/ft32.h: Add R_FT32_15. * opcode/ft32.h: Replace FT32_FLD_K8 with K15. (ft32_shortcode, sc_compar, ft32_split_shortcode, ft32_merge_shortcode, ft32_merge_shortcode): New functions. opcodes/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * opcodes/ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15. * opcodes/ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with K15. Add jmpix pattern. sim/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * sim/ft32/interp.c (step_once): Replace FT32_FLD_K8 with K15.		2017-10-12 18:41:29 -07:00
..
aarch64.h	[AArch64] Add dot product support for AArch64 to binutils	2017-06-28 11:09:01 +01:00
alpha.h
arc-attrs.h	[ARC] Object attributes.	2017-05-10 14:42:22 +02:00
arc-func.h	[ARC] Add JLI support.	2017-07-19 09:56:55 +02:00
arc.h	[ARC] Add SJLI instruction.	2017-07-19 09:56:55 +02:00
arm.h	[ARM] Assembler and disassembler support Dot Product Extension	2017-06-28 11:00:55 +01:00
avr.h	Add support for a __gcc_isr pseudo isntruction to the AVR assembler.	2017-06-30 16:37:39 +01:00
bfin.h
cgen.h
ChangeLog-0415
ChangeLog-9103
convex.h
cr16.h
cris.h
crx.h
d10v.h
d30v.h
dlx.h
ft32.h	FT32: support for FT32B processor - part 1	2017-10-12 18:41:29 -07:00
h8300.h
hppa.h	Fix match and mask for 64-bit bb opcode.	2017-05-14 16:06:06 -04:00
i370.h
i386.h	x86: Add NOTRACK prefix support	2017-05-22 11:02:58 -07:00
i860.h	Clarify that include/opcode/ files are part of GNU opcodes	2017-01-25 12:30:52 +00:00
i960.h
ia64.h
m68hc11.h
m68k.h
m88k.h
metag.h
mips.h	MIPS: Fix XPA base and Virtualization ASE instruction handling	2017-06-30 07:21:55 +01:00
mmix.h
mn10200.h
mn10300.h
moxie.h
msp430-decode.h
msp430.h
nds32.h	nds32: Rename __BIT() to N32_BIT().	2017-09-11 13:46:27 +08:00
nios2.h	Clarify that include/opcode/ files are part of GNU opcodes	2017-01-25 12:30:52 +00:00
nios2r1.h	Clarify that include/opcode/ files are part of GNU opcodes	2017-01-25 12:30:52 +00:00
nios2r2.h	Clarify that include/opcode/ files are part of GNU opcodes	2017-01-25 12:30:52 +00:00
np1.h
ns32k.h
pdp11.h
pj.h
pn.h
ppc.h	[PowerPC VLE] Add SPE2 and EFS2 instructions support	2017-08-24 17:30:31 +09:30
pru.h	Clarify that include/opcode/ files are part of GNU opcodes	2017-01-25 12:30:52 +00:00
pyr.h
riscv-opc.h	RISC-V: Add physical memory protection CSRs	2017-03-31 09:35:11 -07:00
riscv.h
rl78.h
rx.h
s390.h	S/390: Improve error checking for optional operands	2017-05-30 10:22:25 +02:00
score-datadep.h
score-inst.h
sparc.h	binutils: support for the SPARC M8 processor	2017-05-19 09:27:08 -07:00
spu-insns.h
spu.h
tahoe.h
tic4x.h
tic6x-control-registers.h
tic6x-insn-formats.h
tic6x-opcode-table.h
tic6x.h
tic30.h
tic54x.h
tic80.h
tilegx.h
tilepro.h
v850.h	Fix spelling typos.	2017-07-18 16:58:14 +01:00
vax.h
visium.h
wasm.h	Add support for the WebAssembly file format and the wasm32 ELF conversion to gas and the binutils.	2017-03-30 10:57:21 +01:00
xgate.h