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f77bb6c56b
This fixes some EH failures for the medany code model in the g++ testsuite. The problem is that the assembler is computing some values in the eh_frame section as constants, that instead should have had relocs to be resolved by the linker. This happens in output_cfi_insn in the DW_CFA_advance_loc case where it compares label frags and immediately simplifies if they are the same. We can fix that by forcing a new frag after every instruction that the linker can reduce in size. I've also added a testcase to verify the fix. This was tested with binutils make check, and gcc/g++ make checks on qemu for medlow and medany code models. gas/ * config/tc-riscv.c (append_insn): Call frag_wane and frag_new at end for linker optimizable relocs. * testsuite/gas/riscv/eh-relocs.d: New. * testsuite/gas/riscv/eh-relocs.s: New. * testsuite/gas/riscv/riscv.exp: Run eh-relocs test.
2595 lines
69 KiB
C
2595 lines
69 KiB
C
/* tc-riscv.c -- RISC-V assembler
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Copyright (C) 2011-2017 Free Software Foundation, Inc.
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Contributed by Andrew Waterman (andrew@sifive.com).
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Based on MIPS target.
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This file is part of GAS.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#include "as.h"
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#include "config.h"
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#include "subsegs.h"
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#include "safe-ctype.h"
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#include "itbl-ops.h"
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#include "dwarf2dbg.h"
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#include "dw2gencfi.h"
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#include "struc-symbol.h"
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#include "elf/riscv.h"
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#include "opcode/riscv.h"
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#include <stdint.h>
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/* Information about an instruction, including its format, operands
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and fixups. */
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struct riscv_cl_insn
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{
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/* The opcode's entry in riscv_opcodes. */
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const struct riscv_opcode *insn_mo;
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/* The encoded instruction bits. */
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insn_t insn_opcode;
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/* The frag that contains the instruction. */
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struct frag *frag;
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/* The offset into FRAG of the first instruction byte. */
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long where;
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/* The relocs associated with the instruction, if any. */
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fixS *fixp;
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};
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#ifndef DEFAULT_ARCH
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#define DEFAULT_ARCH "riscv64"
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#endif
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static const char default_arch[] = DEFAULT_ARCH;
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static unsigned xlen = 0; /* width of an x-register */
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static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
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#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
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#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
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static unsigned elf_flags = 0;
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/* This is the set of options which the .option pseudo-op may modify. */
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struct riscv_set_options
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{
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int pic; /* Generate position-independent code. */
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int rvc; /* Generate RVC code. */
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int relax; /* Emit relocs the linker is allowed to relax. */
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};
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static struct riscv_set_options riscv_opts =
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{
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0, /* pic */
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0, /* rvc */
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1, /* relax */
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};
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static void
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riscv_set_rvc (bfd_boolean rvc_value)
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{
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if (rvc_value)
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elf_flags |= EF_RISCV_RVC;
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riscv_opts.rvc = rvc_value;
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}
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struct riscv_subset
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{
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const char *name;
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struct riscv_subset *next;
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};
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static struct riscv_subset *riscv_subsets;
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static bfd_boolean
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riscv_subset_supports (const char *feature)
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{
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struct riscv_subset *s;
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char *p;
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unsigned xlen_required = strtoul (feature, &p, 10);
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if (xlen_required && xlen != xlen_required)
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return FALSE;
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for (s = riscv_subsets; s != NULL; s = s->next)
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if (strcasecmp (s->name, p) == 0)
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return TRUE;
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return FALSE;
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}
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static void
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riscv_clear_subsets (void)
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{
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while (riscv_subsets != NULL)
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{
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struct riscv_subset *next = riscv_subsets->next;
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free ((void *) riscv_subsets->name);
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free (riscv_subsets);
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riscv_subsets = next;
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}
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}
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static void
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riscv_add_subset (const char *subset)
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{
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struct riscv_subset *s = xmalloc (sizeof *s);
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s->name = xstrdup (subset);
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s->next = riscv_subsets;
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riscv_subsets = s;
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}
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/* Set which ISA and extensions are available. */
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static void
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riscv_set_arch (const char *s)
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{
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const char *all_subsets = "imafdqc";
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char *extension = NULL;
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const char *p = s;
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riscv_clear_subsets();
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if (strncmp (p, "rv32", 4) == 0)
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{
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xlen = 32;
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p += 4;
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}
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else if (strncmp (p, "rv64", 4) == 0)
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{
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xlen = 64;
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p += 4;
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}
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else
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as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s);
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switch (*p)
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{
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case 'i':
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break;
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case 'g':
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p++;
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for ( ; *all_subsets != 'q'; all_subsets++)
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{
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const char subset[] = {*all_subsets, '\0'};
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riscv_add_subset (subset);
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}
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break;
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default:
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as_fatal ("-march=%s: first ISA subset must be `i' or `g'", s);
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}
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while (*p)
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{
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if (*p == 'x')
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{
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char *subset = xstrdup (p);
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char *q = subset;
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while (*++q != '\0' && *q != '_')
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;
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*q = '\0';
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if (extension)
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as_fatal ("-march=%s: only one non-standard extension is supported"
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" (found `%s' and `%s')", s, extension, subset);
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extension = subset;
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riscv_add_subset (subset);
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p += strlen (subset);
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}
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else if (*p == '_')
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p++;
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else if ((all_subsets = strchr (all_subsets, *p)) != NULL)
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{
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const char subset[] = {*p, 0};
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riscv_add_subset (subset);
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all_subsets++;
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p++;
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}
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else
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as_fatal ("-march=%s: unsupported ISA subset `%c'", s, *p);
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}
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free (extension);
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}
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/* Handle of the OPCODE hash table. */
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static struct hash_control *op_hash = NULL;
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/* This array holds the chars that always start a comment. If the
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pre-processor is disabled, these aren't very useful */
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const char comment_chars[] = "#";
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/* This array holds the chars that only start a comment at the beginning of
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a line. If the line seems to have the form '# 123 filename'
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.line and .file directives will appear in the pre-processed output */
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/* Note that input_file.c hand checks for '#' at the beginning of the
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first line of the input file. This is because the compiler outputs
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#NO_APP at the beginning of its output. */
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/* Also note that C style comments are always supported. */
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const char line_comment_chars[] = "#";
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/* This array holds machine specific line separator characters. */
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const char line_separator_chars[] = ";";
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/* Chars that can be used to separate mant from exp in floating point nums */
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const char EXP_CHARS[] = "eE";
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/* Chars that mean this number is a floating point constant */
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/* As in 0f12.456 */
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/* or 0d1.2345e12 */
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const char FLT_CHARS[] = "rRsSfFdDxXpP";
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/* Macros for encoding relaxation state for RVC branches and far jumps. */
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#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
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((relax_substateT) \
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(0xc0000000 \
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| ((uncond) ? 1 : 0) \
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| ((rvc) ? 2 : 0) \
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| ((length) << 2)))
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#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
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#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
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#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
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#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
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/* Is the given value a sign-extended 32-bit value? */
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#define IS_SEXT_32BIT_NUM(x) \
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(((x) &~ (offsetT) 0x7fffffff) == 0 \
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|| (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
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/* Is the given value a zero-extended 32-bit value? Or a negated one? */
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#define IS_ZEXT_32BIT_NUM(x) \
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(((x) &~ (offsetT) 0xffffffff) == 0 \
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|| (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
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/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
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INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
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#define INSERT_OPERAND(FIELD, INSN, VALUE) \
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INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
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/* Determine if an instruction matches an opcode. */
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#define OPCODE_MATCHES(OPCODE, OP) \
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(((OPCODE) & MASK_##OP) == MATCH_##OP)
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static char *expr_end;
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/* The default target format to use. */
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const char *
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riscv_target_format (void)
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{
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return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
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}
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/* Return the length of instruction INSN. */
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static inline unsigned int
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insn_length (const struct riscv_cl_insn *insn)
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{
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return riscv_insn_length (insn->insn_opcode);
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}
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/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
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static void
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create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
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{
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insn->insn_mo = mo;
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insn->insn_opcode = mo->match;
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insn->frag = NULL;
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insn->where = 0;
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insn->fixp = NULL;
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}
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/* Install INSN at the location specified by its "frag" and "where" fields. */
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static void
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install_insn (const struct riscv_cl_insn *insn)
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{
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char *f = insn->frag->fr_literal + insn->where;
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md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
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}
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/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
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and install the opcode in the new location. */
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static void
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move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
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{
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insn->frag = frag;
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insn->where = where;
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if (insn->fixp != NULL)
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{
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insn->fixp->fx_frag = frag;
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insn->fixp->fx_where = where;
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}
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install_insn (insn);
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}
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/* Add INSN to the end of the output. */
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static void
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add_fixed_insn (struct riscv_cl_insn *insn)
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{
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char *f = frag_more (insn_length (insn));
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move_insn (insn, frag_now, f - frag_now->fr_literal);
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}
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static void
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add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
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relax_substateT subtype, symbolS *symbol, offsetT offset)
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{
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frag_grow (max_chars);
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move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
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frag_var (rs_machine_dependent, max_chars, var,
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subtype, symbol, offset, NULL);
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}
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/* Compute the length of a branch sequence, and adjust the stored length
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accordingly. If FRAGP is NULL, the worst-case length is returned. */
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static unsigned
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relaxed_branch_length (fragS *fragp, asection *sec, int update)
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{
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int jump, rvc, length = 8;
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if (!fragp)
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return length;
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jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
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rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
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length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
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/* Assume jumps are in range; the linker will catch any that aren't. */
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length = jump ? 4 : 8;
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if (fragp->fr_symbol != NULL
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&& S_IS_DEFINED (fragp->fr_symbol)
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&& !S_IS_WEAK (fragp->fr_symbol)
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&& sec == S_GET_SEGMENT (fragp->fr_symbol))
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{
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offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
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bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
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val -= fragp->fr_address + fragp->fr_fix;
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if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
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length = 2;
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else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
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length = 4;
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else if (!jump && rvc)
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length = 6;
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}
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if (update)
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fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
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return length;
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}
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struct regname
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{
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const char *name;
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unsigned int num;
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};
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enum reg_class
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{
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RCLASS_GPR,
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RCLASS_FPR,
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RCLASS_CSR,
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RCLASS_MAX
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};
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static struct hash_control *reg_names_hash = NULL;
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#define ENCODE_REG_HASH(cls, n) \
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((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
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#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
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#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
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static void
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hash_reg_name (enum reg_class class, const char *name, unsigned n)
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{
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void *hash = ENCODE_REG_HASH (class, n);
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const char *retval = hash_insert (reg_names_hash, name, hash);
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if (retval != NULL)
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as_fatal (_("internal error: can't hash `%s': %s"), name, retval);
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}
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static void
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hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
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{
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unsigned i;
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for (i = 0; i < n; i++)
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hash_reg_name (class, names[i], i);
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}
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static unsigned int
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reg_lookup_internal (const char *s, enum reg_class class)
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{
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struct regname *r = (struct regname *) hash_find (reg_names_hash, s);
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if (r == NULL || DECODE_REG_CLASS (r) != class)
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return -1;
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return DECODE_REG_NUM (r);
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}
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static bfd_boolean
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reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
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{
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char *e;
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char save_c;
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int reg = -1;
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/* Find end of name. */
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e = *s;
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if (is_name_beginner (*e))
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++e;
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while (is_part_of_name (*e))
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++e;
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/* Terminate name. */
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save_c = *e;
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*e = '\0';
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/* Look for the register. Advance to next token if one was recognized. */
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if ((reg = reg_lookup_internal (*s, class)) >= 0)
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*s = e;
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*e = save_c;
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if (regnop)
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*regnop = reg;
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return reg >= 0;
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}
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static bfd_boolean
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arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
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{
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const char *p = strchr (*s, ',');
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size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
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for (i = 0; i < size; i++)
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if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
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{
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*regnop = i;
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*s += len;
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return TRUE;
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}
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return FALSE;
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}
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/* For consistency checking, verify that all bits are specified either
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by the match/mask part of the instruction definition, or by the
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operand list. */
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static bfd_boolean
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validate_riscv_insn (const struct riscv_opcode *opc)
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{
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const char *p = opc->args;
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char c;
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insn_t used_bits = opc->mask;
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int insn_width = 8 * riscv_insn_length (opc->match);
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insn_t required_bits = ~0ULL >> (64 - insn_width);
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if ((used_bits & opc->match) != (opc->match & required_bits))
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{
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as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
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opc->name, opc->args);
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return FALSE;
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}
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|
|
|
#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
|
|
while (*p)
|
|
switch (c = *p++)
|
|
{
|
|
case 'C': /* RVC */
|
|
switch (c = *p++)
|
|
{
|
|
case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
|
|
case 'c': break; /* RS1, constrained to equal sp */
|
|
case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
|
|
case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
|
|
case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
|
|
case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
|
|
case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
|
|
case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
|
|
case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
|
|
case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
|
|
case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
|
|
case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
|
|
case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
|
|
case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
|
|
case 'w': break; /* RS1S, constrained to equal RD */
|
|
case 'x': break; /* RS2S, constrained to equal RD */
|
|
case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
|
|
case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
|
|
case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
|
|
case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
|
|
case 'U': break; /* RS1, constrained to equal RD */
|
|
case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
|
|
case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
|
|
case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
|
|
case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
|
|
case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
|
|
default:
|
|
as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
|
|
c, opc->name, opc->args);
|
|
return FALSE;
|
|
}
|
|
break;
|
|
case ',': break;
|
|
case '(': break;
|
|
case ')': break;
|
|
case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
|
|
case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
|
|
case 'A': break;
|
|
case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
|
|
case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
|
|
case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
|
|
case 'I': break;
|
|
case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
|
|
case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
|
|
case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */
|
|
case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
|
|
case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
|
|
case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
|
|
case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
|
|
case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
|
|
case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
|
|
case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
|
|
case 'o':
|
|
case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
|
|
case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
|
|
case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
|
|
case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
|
|
case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
|
|
case '[': break;
|
|
case ']': break;
|
|
case '0': break;
|
|
default:
|
|
as_bad (_("internal: bad RISC-V opcode "
|
|
"(unknown operand type `%c'): %s %s"),
|
|
c, opc->name, opc->args);
|
|
return FALSE;
|
|
}
|
|
#undef USE_BITS
|
|
if (used_bits != required_bits)
|
|
{
|
|
as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
|
|
~(unsigned long)(used_bits & required_bits),
|
|
opc->name, opc->args);
|
|
return FALSE;
|
|
}
|
|
return TRUE;
|
|
}
|
|
|
|
struct percent_op_match
|
|
{
|
|
const char *str;
|
|
bfd_reloc_code_real_type reloc;
|
|
};
|
|
|
|
/* This function is called once, at assembler startup time. It should set up
|
|
all the tables, etc. that the MD part of the assembler will need. */
|
|
|
|
void
|
|
md_begin (void)
|
|
{
|
|
int i = 0;
|
|
unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
|
|
|
|
if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
|
|
as_warn (_("Could not set architecture and machine"));
|
|
|
|
op_hash = hash_new ();
|
|
|
|
while (riscv_opcodes[i].name)
|
|
{
|
|
const char *name = riscv_opcodes[i].name;
|
|
const char *hash_error =
|
|
hash_insert (op_hash, name, (void *) &riscv_opcodes[i]);
|
|
|
|
if (hash_error)
|
|
{
|
|
fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
|
|
riscv_opcodes[i].name, hash_error);
|
|
/* Probably a memory allocation problem? Give up now. */
|
|
as_fatal (_("Broken assembler. No assembly attempted."));
|
|
}
|
|
|
|
do
|
|
{
|
|
if (riscv_opcodes[i].pinfo != INSN_MACRO)
|
|
{
|
|
if (!validate_riscv_insn (&riscv_opcodes[i]))
|
|
as_fatal (_("Broken assembler. No assembly attempted."));
|
|
}
|
|
++i;
|
|
}
|
|
while (riscv_opcodes[i].name && !strcmp (riscv_opcodes[i].name, name));
|
|
}
|
|
|
|
reg_names_hash = hash_new ();
|
|
hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
|
|
hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
|
|
hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
|
|
hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
|
|
|
|
#define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
|
|
#define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
|
|
#include "opcode/riscv-opc.h"
|
|
#undef DECLARE_CSR
|
|
|
|
/* Set the default alignment for the text section. */
|
|
record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
|
|
}
|
|
|
|
static insn_t
|
|
riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
|
|
{
|
|
switch (reloc_type)
|
|
{
|
|
case BFD_RELOC_32:
|
|
return value;
|
|
|
|
case BFD_RELOC_RISCV_HI20:
|
|
return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
|
|
|
|
case BFD_RELOC_RISCV_LO12_S:
|
|
return ENCODE_STYPE_IMM (value);
|
|
|
|
case BFD_RELOC_RISCV_LO12_I:
|
|
return ENCODE_ITYPE_IMM (value);
|
|
|
|
default:
|
|
abort ();
|
|
}
|
|
}
|
|
|
|
/* Output an instruction. IP is the instruction information.
|
|
ADDRESS_EXPR is an operand of the instruction to be used with
|
|
RELOC_TYPE. */
|
|
|
|
static void
|
|
append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
|
|
bfd_reloc_code_real_type reloc_type)
|
|
{
|
|
dwarf2_emit_insn (0);
|
|
|
|
if (reloc_type != BFD_RELOC_UNUSED)
|
|
{
|
|
reloc_howto_type *howto;
|
|
|
|
gas_assert (address_expr);
|
|
if (reloc_type == BFD_RELOC_12_PCREL
|
|
|| reloc_type == BFD_RELOC_RISCV_JMP)
|
|
{
|
|
int j = reloc_type == BFD_RELOC_RISCV_JMP;
|
|
int best_case = riscv_insn_length (ip->insn_opcode);
|
|
unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
|
|
add_relaxed_insn (ip, worst_case, best_case,
|
|
RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
|
|
address_expr->X_add_symbol,
|
|
address_expr->X_add_number);
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
|
|
if (howto == NULL)
|
|
as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
|
|
|
|
ip->fixp = fix_new_exp (ip->frag, ip->where,
|
|
bfd_get_reloc_size (howto),
|
|
address_expr, FALSE, reloc_type);
|
|
|
|
ip->fixp->fx_tcbit = riscv_opts.relax;
|
|
}
|
|
}
|
|
|
|
add_fixed_insn (ip);
|
|
install_insn (ip);
|
|
|
|
/* We need to start a new frag after any instruction that can be
|
|
optimized away or compressed by the linker during relaxation, to prevent
|
|
the assembler from computing static offsets across such an instruction.
|
|
This is necessary to get correct EH info. */
|
|
if (reloc_type == BFD_RELOC_RISCV_CALL
|
|
|| reloc_type == BFD_RELOC_RISCV_CALL_PLT
|
|
|| reloc_type == BFD_RELOC_RISCV_HI20
|
|
|| reloc_type == BFD_RELOC_RISCV_PCREL_HI20
|
|
|| reloc_type == BFD_RELOC_RISCV_TPREL_HI20
|
|
|| reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
|
|
{
|
|
frag_wane (frag_now);
|
|
frag_new (0);
|
|
}
|
|
}
|
|
|
|
/* Build an instruction created by a macro expansion. This is passed
|
|
a pointer to the count of instructions created so far, an
|
|
expression, the name of the instruction to build, an operand format
|
|
string, and corresponding arguments. */
|
|
|
|
static void
|
|
macro_build (expressionS *ep, const char *name, const char *fmt, ...)
|
|
{
|
|
const struct riscv_opcode *mo;
|
|
struct riscv_cl_insn insn;
|
|
bfd_reloc_code_real_type r;
|
|
va_list args;
|
|
|
|
va_start (args, fmt);
|
|
|
|
r = BFD_RELOC_UNUSED;
|
|
mo = (struct riscv_opcode *) hash_find (op_hash, name);
|
|
gas_assert (mo);
|
|
|
|
/* Find a non-RVC variant of the instruction. append_insn will compress
|
|
it if possible. */
|
|
while (riscv_insn_length (mo->match) < 4)
|
|
mo++;
|
|
gas_assert (strcmp (name, mo->name) == 0);
|
|
|
|
create_insn (&insn, mo);
|
|
for (;;)
|
|
{
|
|
switch (*fmt++)
|
|
{
|
|
case 'd':
|
|
INSERT_OPERAND (RD, insn, va_arg (args, int));
|
|
continue;
|
|
|
|
case 's':
|
|
INSERT_OPERAND (RS1, insn, va_arg (args, int));
|
|
continue;
|
|
|
|
case 't':
|
|
INSERT_OPERAND (RS2, insn, va_arg (args, int));
|
|
continue;
|
|
|
|
case '>':
|
|
INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
|
|
continue;
|
|
|
|
case 'j':
|
|
case 'u':
|
|
case 'q':
|
|
gas_assert (ep != NULL);
|
|
r = va_arg (args, int);
|
|
continue;
|
|
|
|
case '\0':
|
|
break;
|
|
case ',':
|
|
continue;
|
|
default:
|
|
as_fatal (_("internal error: invalid macro"));
|
|
}
|
|
break;
|
|
}
|
|
va_end (args);
|
|
gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
|
|
|
|
append_insn (&insn, ep, r);
|
|
}
|
|
|
|
/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
|
|
unset. */
|
|
static void
|
|
normalize_constant_expr (expressionS *ex)
|
|
{
|
|
if (xlen > 32)
|
|
return;
|
|
if ((ex->X_op == O_constant || ex->X_op == O_symbol)
|
|
&& IS_ZEXT_32BIT_NUM (ex->X_add_number))
|
|
ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
|
|
- 0x80000000);
|
|
}
|
|
|
|
/* Fail if an expression is not a constant. */
|
|
|
|
static void
|
|
check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex)
|
|
{
|
|
if (ex->X_op == O_big)
|
|
as_bad (_("unsupported large constant"));
|
|
else if (ex->X_op != O_constant)
|
|
as_bad (_("Instruction %s requires absolute expression"),
|
|
ip->insn_mo->name);
|
|
normalize_constant_expr (ex);
|
|
}
|
|
|
|
static symbolS *
|
|
make_internal_label (void)
|
|
{
|
|
return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg,
|
|
(valueT) frag_now_fix (), frag_now);
|
|
}
|
|
|
|
/* Load an entry from the GOT. */
|
|
static void
|
|
pcrel_access (int destreg, int tempreg, expressionS *ep,
|
|
const char *lo_insn, const char *lo_pattern,
|
|
bfd_reloc_code_real_type hi_reloc,
|
|
bfd_reloc_code_real_type lo_reloc)
|
|
{
|
|
expressionS ep2;
|
|
ep2.X_op = O_symbol;
|
|
ep2.X_add_symbol = make_internal_label ();
|
|
ep2.X_add_number = 0;
|
|
|
|
macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
|
|
macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
|
|
}
|
|
|
|
static void
|
|
pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
|
|
bfd_reloc_code_real_type hi_reloc,
|
|
bfd_reloc_code_real_type lo_reloc)
|
|
{
|
|
pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
|
|
}
|
|
|
|
static void
|
|
pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
|
|
bfd_reloc_code_real_type hi_reloc,
|
|
bfd_reloc_code_real_type lo_reloc)
|
|
{
|
|
pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
|
|
}
|
|
|
|
/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
|
|
static void
|
|
riscv_call (int destreg, int tempreg, expressionS *ep,
|
|
bfd_reloc_code_real_type reloc)
|
|
{
|
|
macro_build (ep, "auipc", "d,u", tempreg, reloc);
|
|
macro_build (NULL, "jalr", "d,s", destreg, tempreg);
|
|
}
|
|
|
|
/* Load an integer constant into a register. */
|
|
|
|
static void
|
|
load_const (int reg, expressionS *ep)
|
|
{
|
|
int shift = RISCV_IMM_BITS;
|
|
expressionS upper = *ep, lower = *ep;
|
|
lower.X_add_number = (int32_t) ep->X_add_number << (32-shift) >> (32-shift);
|
|
upper.X_add_number -= lower.X_add_number;
|
|
|
|
if (ep->X_op != O_constant)
|
|
{
|
|
as_bad (_("unsupported large constant"));
|
|
return;
|
|
}
|
|
|
|
if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
|
|
{
|
|
/* Reduce to a signed 32-bit constant using SLLI and ADDI. */
|
|
while (((upper.X_add_number >> shift) & 1) == 0)
|
|
shift++;
|
|
|
|
upper.X_add_number = (int64_t) upper.X_add_number >> shift;
|
|
load_const (reg, &upper);
|
|
|
|
macro_build (NULL, "slli", "d,s,>", reg, reg, shift);
|
|
if (lower.X_add_number != 0)
|
|
macro_build (&lower, "addi", "d,s,j", reg, reg, BFD_RELOC_RISCV_LO12_I);
|
|
}
|
|
else
|
|
{
|
|
/* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
|
|
int hi_reg = 0;
|
|
|
|
if (upper.X_add_number != 0)
|
|
{
|
|
macro_build (ep, "lui", "d,u", reg, BFD_RELOC_RISCV_HI20);
|
|
hi_reg = reg;
|
|
}
|
|
|
|
if (lower.X_add_number != 0 || hi_reg == 0)
|
|
macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg,
|
|
BFD_RELOC_RISCV_LO12_I);
|
|
}
|
|
}
|
|
|
|
/* Expand RISC-V assembly macros into one or more instructions. */
|
|
static void
|
|
macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
|
|
bfd_reloc_code_real_type *imm_reloc)
|
|
{
|
|
int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
|
|
int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
|
|
int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
|
|
int mask = ip->insn_mo->mask;
|
|
|
|
switch (mask)
|
|
{
|
|
case M_LI:
|
|
load_const (rd, imm_expr);
|
|
break;
|
|
|
|
case M_LA:
|
|
case M_LLA:
|
|
/* Load the address of a symbol into a register. */
|
|
if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
|
|
as_bad (_("offset too large"));
|
|
|
|
if (imm_expr->X_op == O_constant)
|
|
load_const (rd, imm_expr);
|
|
else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */
|
|
pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
|
|
BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
|
else /* Local PIC symbol, or any non-PIC symbol */
|
|
pcrel_load (rd, rd, imm_expr, "addi",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
|
break;
|
|
|
|
case M_LA_TLS_GD:
|
|
pcrel_load (rd, rd, imm_expr, "addi",
|
|
BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
|
break;
|
|
|
|
case M_LA_TLS_IE:
|
|
pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
|
|
BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
|
break;
|
|
|
|
case M_LB:
|
|
pcrel_load (rd, rd, imm_expr, "lb",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
|
break;
|
|
|
|
case M_LBU:
|
|
pcrel_load (rd, rd, imm_expr, "lbu",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
|
break;
|
|
|
|
case M_LH:
|
|
pcrel_load (rd, rd, imm_expr, "lh",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
|
break;
|
|
|
|
case M_LHU:
|
|
pcrel_load (rd, rd, imm_expr, "lhu",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
|
break;
|
|
|
|
case M_LW:
|
|
pcrel_load (rd, rd, imm_expr, "lw",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
|
break;
|
|
|
|
case M_LWU:
|
|
pcrel_load (rd, rd, imm_expr, "lwu",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
|
break;
|
|
|
|
case M_LD:
|
|
pcrel_load (rd, rd, imm_expr, "ld",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
|
break;
|
|
|
|
case M_FLW:
|
|
pcrel_load (rd, rs1, imm_expr, "flw",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
|
break;
|
|
|
|
case M_FLD:
|
|
pcrel_load (rd, rs1, imm_expr, "fld",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
|
|
break;
|
|
|
|
case M_SB:
|
|
pcrel_store (rs2, rs1, imm_expr, "sb",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
|
|
break;
|
|
|
|
case M_SH:
|
|
pcrel_store (rs2, rs1, imm_expr, "sh",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
|
|
break;
|
|
|
|
case M_SW:
|
|
pcrel_store (rs2, rs1, imm_expr, "sw",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
|
|
break;
|
|
|
|
case M_SD:
|
|
pcrel_store (rs2, rs1, imm_expr, "sd",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
|
|
break;
|
|
|
|
case M_FSW:
|
|
pcrel_store (rs2, rs1, imm_expr, "fsw",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
|
|
break;
|
|
|
|
case M_FSD:
|
|
pcrel_store (rs2, rs1, imm_expr, "fsd",
|
|
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
|
|
break;
|
|
|
|
case M_CALL:
|
|
riscv_call (rd, rs1, imm_expr, *imm_reloc);
|
|
break;
|
|
|
|
default:
|
|
as_bad (_("Macro %s not implemented"), ip->insn_mo->name);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static const struct percent_op_match percent_op_utype[] =
|
|
{
|
|
{"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
|
|
{"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
|
|
{"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
|
|
{"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
|
|
{"%hi", BFD_RELOC_RISCV_HI20},
|
|
{0, 0}
|
|
};
|
|
|
|
static const struct percent_op_match percent_op_itype[] =
|
|
{
|
|
{"%lo", BFD_RELOC_RISCV_LO12_I},
|
|
{"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
|
|
{"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
|
|
{0, 0}
|
|
};
|
|
|
|
static const struct percent_op_match percent_op_stype[] =
|
|
{
|
|
{"%lo", BFD_RELOC_RISCV_LO12_S},
|
|
{"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
|
|
{"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
|
|
{0, 0}
|
|
};
|
|
|
|
static const struct percent_op_match percent_op_rtype[] =
|
|
{
|
|
{"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
|
|
{0, 0}
|
|
};
|
|
|
|
/* Return true if *STR points to a relocation operator. When returning true,
|
|
move *STR over the operator and store its relocation code in *RELOC.
|
|
Leave both *STR and *RELOC alone when returning false. */
|
|
|
|
static bfd_boolean
|
|
parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
|
|
const struct percent_op_match *percent_op)
|
|
{
|
|
for ( ; percent_op->str; percent_op++)
|
|
if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
|
|
{
|
|
int len = strlen (percent_op->str);
|
|
|
|
if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
|
|
continue;
|
|
|
|
*str += strlen (percent_op->str);
|
|
*reloc = percent_op->reloc;
|
|
|
|
/* Check whether the output BFD supports this relocation.
|
|
If not, issue an error and fall back on something safe. */
|
|
if (*reloc != BFD_RELOC_UNUSED
|
|
&& !bfd_reloc_type_lookup (stdoutput, *reloc))
|
|
{
|
|
as_bad ("relocation %s isn't supported by the current ABI",
|
|
percent_op->str);
|
|
*reloc = BFD_RELOC_UNUSED;
|
|
}
|
|
return TRUE;
|
|
}
|
|
return FALSE;
|
|
}
|
|
|
|
static void
|
|
my_getExpression (expressionS *ep, char *str)
|
|
{
|
|
char *save_in;
|
|
|
|
save_in = input_line_pointer;
|
|
input_line_pointer = str;
|
|
expression (ep);
|
|
expr_end = input_line_pointer;
|
|
input_line_pointer = save_in;
|
|
}
|
|
|
|
/* Parse string STR as a 16-bit relocatable operand. Store the
|
|
expression in *EP and the relocation, if any, in RELOC.
|
|
Return the number of relocation operators used (0 or 1).
|
|
|
|
On exit, EXPR_END points to the first character after the expression. */
|
|
|
|
static size_t
|
|
my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
|
|
char *str, const struct percent_op_match *percent_op)
|
|
{
|
|
size_t reloc_index;
|
|
unsigned crux_depth, str_depth, regno;
|
|
char *crux;
|
|
|
|
/* First, check for integer registers. */
|
|
if (reg_lookup (&str, RCLASS_GPR, ®no))
|
|
{
|
|
ep->X_op = O_register;
|
|
ep->X_add_number = regno;
|
|
return 0;
|
|
}
|
|
|
|
/* Search for the start of the main expression.
|
|
End the loop with CRUX pointing to the start
|
|
of the main expression and with CRUX_DEPTH containing the number
|
|
of open brackets at that point. */
|
|
reloc_index = -1;
|
|
str_depth = 0;
|
|
do
|
|
{
|
|
reloc_index++;
|
|
crux = str;
|
|
crux_depth = str_depth;
|
|
|
|
/* Skip over whitespace and brackets, keeping count of the number
|
|
of brackets. */
|
|
while (*str == ' ' || *str == '\t' || *str == '(')
|
|
if (*str++ == '(')
|
|
str_depth++;
|
|
}
|
|
while (*str == '%'
|
|
&& reloc_index < 1
|
|
&& parse_relocation (&str, reloc, percent_op));
|
|
|
|
my_getExpression (ep, crux);
|
|
str = expr_end;
|
|
|
|
/* Match every open bracket. */
|
|
while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
|
|
if (*str++ == ')')
|
|
crux_depth--;
|
|
|
|
if (crux_depth > 0)
|
|
as_bad ("unclosed '('");
|
|
|
|
expr_end = str;
|
|
|
|
return reloc_index;
|
|
}
|
|
|
|
/* This routine assembles an instruction into its binary format. As a
|
|
side effect, it sets the global variable imm_reloc to the type of
|
|
relocation to do if one of the operands is an address expression. */
|
|
|
|
static const char *
|
|
riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
|
|
bfd_reloc_code_real_type *imm_reloc)
|
|
{
|
|
char *s;
|
|
const char *args;
|
|
char c = 0;
|
|
struct riscv_opcode *insn;
|
|
char *argsStart;
|
|
unsigned int regno;
|
|
char save_c = 0;
|
|
int argnum;
|
|
const struct percent_op_match *p;
|
|
const char *error = "unrecognized opcode";
|
|
|
|
/* Parse the name of the instruction. Terminate the string if whitespace
|
|
is found so that hash_find only sees the name part of the string. */
|
|
for (s = str; *s != '\0'; ++s)
|
|
if (ISSPACE (*s))
|
|
{
|
|
save_c = *s;
|
|
*s++ = '\0';
|
|
break;
|
|
}
|
|
|
|
insn = (struct riscv_opcode *) hash_find (op_hash, str);
|
|
|
|
argsStart = s;
|
|
for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
|
|
{
|
|
if (!riscv_subset_supports (insn->subset))
|
|
continue;
|
|
|
|
create_insn (ip, insn);
|
|
argnum = 1;
|
|
|
|
imm_expr->X_op = O_absent;
|
|
*imm_reloc = BFD_RELOC_UNUSED;
|
|
p = percent_op_itype;
|
|
|
|
for (args = insn->args;; ++args)
|
|
{
|
|
s += strspn (s, " \t");
|
|
switch (*args)
|
|
{
|
|
case '\0': /* End of args. */
|
|
if (insn->pinfo != INSN_MACRO)
|
|
{
|
|
if (!insn->match_func (insn, ip->insn_opcode))
|
|
break;
|
|
if (riscv_insn_length (insn->match) == 2 && !riscv_opts.rvc)
|
|
break;
|
|
}
|
|
if (*s != '\0')
|
|
break;
|
|
/* Successful assembly. */
|
|
error = NULL;
|
|
goto out;
|
|
|
|
case 'C': /* RVC */
|
|
switch (*++args)
|
|
{
|
|
case 's': /* RS1 x8-x15 */
|
|
if (!reg_lookup (&s, RCLASS_GPR, ®no)
|
|
|| !(regno >= 8 && regno <= 15))
|
|
break;
|
|
INSERT_OPERAND (CRS1S, *ip, regno % 8);
|
|
continue;
|
|
case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
|
|
if (!reg_lookup (&s, RCLASS_GPR, ®no)
|
|
|| EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
|
|
break;
|
|
continue;
|
|
case 't': /* RS2 x8-x15 */
|
|
if (!reg_lookup (&s, RCLASS_GPR, ®no)
|
|
|| !(regno >= 8 && regno <= 15))
|
|
break;
|
|
INSERT_OPERAND (CRS2S, *ip, regno % 8);
|
|
continue;
|
|
case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
|
|
if (!reg_lookup (&s, RCLASS_GPR, ®no)
|
|
|| EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
|
|
break;
|
|
continue;
|
|
case 'U': /* RS1, constrained to equal RD. */
|
|
if (!reg_lookup (&s, RCLASS_GPR, ®no)
|
|
|| EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
|
|
break;
|
|
continue;
|
|
case 'V': /* RS2 */
|
|
if (!reg_lookup (&s, RCLASS_GPR, ®no))
|
|
break;
|
|
INSERT_OPERAND (CRS2, *ip, regno);
|
|
continue;
|
|
case 'c': /* RS1, constrained to equal sp. */
|
|
if (!reg_lookup (&s, RCLASS_GPR, ®no)
|
|
|| regno != X_SP)
|
|
break;
|
|
continue;
|
|
case '>':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| imm_expr->X_op != O_constant
|
|
|| imm_expr->X_add_number <= 0
|
|
|| imm_expr->X_add_number >= 64)
|
|
break;
|
|
ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
|
|
rvc_imm_done:
|
|
s = expr_end;
|
|
imm_expr->X_op = O_absent;
|
|
continue;
|
|
case '<':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| imm_expr->X_op != O_constant
|
|
|| !VALID_RVC_IMM (imm_expr->X_add_number)
|
|
|| imm_expr->X_add_number <= 0
|
|
|| imm_expr->X_add_number >= 32)
|
|
break;
|
|
ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
|
|
goto rvc_imm_done;
|
|
case 'i':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| imm_expr->X_op != O_constant
|
|
|| imm_expr->X_add_number == 0
|
|
|| !VALID_RVC_SIMM3 (imm_expr->X_add_number))
|
|
break;
|
|
ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
|
|
goto rvc_imm_done;
|
|
case 'j':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| imm_expr->X_op != O_constant
|
|
|| imm_expr->X_add_number == 0
|
|
|| !VALID_RVC_IMM (imm_expr->X_add_number))
|
|
break;
|
|
ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
|
|
goto rvc_imm_done;
|
|
case 'k':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| imm_expr->X_op != O_constant
|
|
|| !VALID_RVC_LW_IMM (imm_expr->X_add_number))
|
|
break;
|
|
ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
|
|
goto rvc_imm_done;
|
|
case 'l':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| imm_expr->X_op != O_constant
|
|
|| !VALID_RVC_LD_IMM (imm_expr->X_add_number))
|
|
break;
|
|
ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
|
|
goto rvc_imm_done;
|
|
case 'm':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| imm_expr->X_op != O_constant
|
|
|| !VALID_RVC_LWSP_IMM (imm_expr->X_add_number))
|
|
break;
|
|
ip->insn_opcode |=
|
|
ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
|
|
goto rvc_imm_done;
|
|
case 'n':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| imm_expr->X_op != O_constant
|
|
|| !VALID_RVC_LDSP_IMM (imm_expr->X_add_number))
|
|
break;
|
|
ip->insn_opcode |=
|
|
ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
|
|
goto rvc_imm_done;
|
|
case 'o':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| imm_expr->X_op != O_constant
|
|
|| !VALID_RVC_IMM (imm_expr->X_add_number))
|
|
break;
|
|
ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
|
|
goto rvc_imm_done;
|
|
case 'K':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| imm_expr->X_op != O_constant
|
|
|| !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number)
|
|
|| imm_expr->X_add_number == 0)
|
|
break;
|
|
ip->insn_opcode |=
|
|
ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
|
|
goto rvc_imm_done;
|
|
case 'L':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| imm_expr->X_op != O_constant
|
|
|| !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number)
|
|
|| imm_expr->X_add_number == 0)
|
|
break;
|
|
ip->insn_opcode |=
|
|
ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
|
|
goto rvc_imm_done;
|
|
case 'M':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| imm_expr->X_op != O_constant
|
|
|| !VALID_RVC_SWSP_IMM (imm_expr->X_add_number))
|
|
break;
|
|
ip->insn_opcode |=
|
|
ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
|
|
goto rvc_imm_done;
|
|
case 'N':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| imm_expr->X_op != O_constant
|
|
|| !VALID_RVC_SDSP_IMM (imm_expr->X_add_number))
|
|
break;
|
|
ip->insn_opcode |=
|
|
ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
|
|
goto rvc_imm_done;
|
|
case 'u':
|
|
p = percent_op_utype;
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
|
|
break;
|
|
rvc_lui:
|
|
if (imm_expr->X_op != O_constant
|
|
|| imm_expr->X_add_number <= 0
|
|
|| imm_expr->X_add_number >= RISCV_BIGIMM_REACH
|
|
|| (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
|
|
&& (imm_expr->X_add_number <
|
|
RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
|
|
break;
|
|
ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
|
|
goto rvc_imm_done;
|
|
case 'v':
|
|
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
|| (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
|
|
|| ((int32_t)imm_expr->X_add_number
|
|
!= imm_expr->X_add_number))
|
|
break;
|
|
imm_expr->X_add_number =
|
|
((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
|
|
goto rvc_lui;
|
|
case 'p':
|
|
goto branch;
|
|
case 'a':
|
|
goto jump;
|
|
case 'D': /* Floating-point RS2 x8-x15. */
|
|
if (!reg_lookup (&s, RCLASS_FPR, ®no)
|
|
|| !(regno >= 8 && regno <= 15))
|
|
break;
|
|
INSERT_OPERAND (CRS2S, *ip, regno % 8);
|
|
continue;
|
|
case 'T': /* Floating-point RS2. */
|
|
if (!reg_lookup (&s, RCLASS_FPR, ®no))
|
|
break;
|
|
INSERT_OPERAND (CRS2, *ip, regno);
|
|
continue;
|
|
default:
|
|
as_bad (_("bad RVC field specifier 'C%c'\n"), *args);
|
|
}
|
|
break;
|
|
|
|
case ',':
|
|
++argnum;
|
|
if (*s++ == *args)
|
|
continue;
|
|
s--;
|
|
break;
|
|
|
|
case '(':
|
|
case ')':
|
|
case '[':
|
|
case ']':
|
|
if (*s++ == *args)
|
|
continue;
|
|
break;
|
|
|
|
case '<': /* Shift amount, 0 - 31. */
|
|
my_getExpression (imm_expr, s);
|
|
check_absolute_expr (ip, imm_expr);
|
|
if ((unsigned long) imm_expr->X_add_number > 31)
|
|
as_bad (_("Improper shift amount (%lu)"),
|
|
(unsigned long) imm_expr->X_add_number);
|
|
INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
|
|
imm_expr->X_op = O_absent;
|
|
s = expr_end;
|
|
continue;
|
|
|
|
case '>': /* Shift amount, 0 - (XLEN-1). */
|
|
my_getExpression (imm_expr, s);
|
|
check_absolute_expr (ip, imm_expr);
|
|
if ((unsigned long) imm_expr->X_add_number >= xlen)
|
|
as_bad (_("Improper shift amount (%lu)"),
|
|
(unsigned long) imm_expr->X_add_number);
|
|
INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
|
|
imm_expr->X_op = O_absent;
|
|
s = expr_end;
|
|
continue;
|
|
|
|
case 'Z': /* CSRRxI immediate. */
|
|
my_getExpression (imm_expr, s);
|
|
check_absolute_expr (ip, imm_expr);
|
|
if ((unsigned long) imm_expr->X_add_number > 31)
|
|
as_bad (_("Improper CSRxI immediate (%lu)"),
|
|
(unsigned long) imm_expr->X_add_number);
|
|
INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
|
|
imm_expr->X_op = O_absent;
|
|
s = expr_end;
|
|
continue;
|
|
|
|
case 'E': /* Control register. */
|
|
if (reg_lookup (&s, RCLASS_CSR, ®no))
|
|
INSERT_OPERAND (CSR, *ip, regno);
|
|
else
|
|
{
|
|
my_getExpression (imm_expr, s);
|
|
check_absolute_expr (ip, imm_expr);
|
|
if ((unsigned long) imm_expr->X_add_number > 0xfff)
|
|
as_bad (_("Improper CSR address (%lu)"),
|
|
(unsigned long) imm_expr->X_add_number);
|
|
INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
|
|
imm_expr->X_op = O_absent;
|
|
s = expr_end;
|
|
}
|
|
continue;
|
|
|
|
case 'm': /* Rounding mode. */
|
|
if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), ®no))
|
|
{
|
|
INSERT_OPERAND (RM, *ip, regno);
|
|
continue;
|
|
}
|
|
break;
|
|
|
|
case 'P':
|
|
case 'Q': /* Fence predecessor/successor. */
|
|
if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
|
|
®no))
|
|
{
|
|
if (*args == 'P')
|
|
INSERT_OPERAND (PRED, *ip, regno);
|
|
else
|
|
INSERT_OPERAND (SUCC, *ip, regno);
|
|
continue;
|
|
}
|
|
break;
|
|
|
|
case 'd': /* Destination register. */
|
|
case 's': /* Source register. */
|
|
case 't': /* Target register. */
|
|
if (reg_lookup (&s, RCLASS_GPR, ®no))
|
|
{
|
|
c = *args;
|
|
if (*s == ' ')
|
|
++s;
|
|
|
|
/* Now that we have assembled one operand, we use the args
|
|
string to figure out where it goes in the instruction. */
|
|
switch (c)
|
|
{
|
|
case 's':
|
|
INSERT_OPERAND (RS1, *ip, regno);
|
|
break;
|
|
case 'd':
|
|
INSERT_OPERAND (RD, *ip, regno);
|
|
break;
|
|
case 't':
|
|
INSERT_OPERAND (RS2, *ip, regno);
|
|
break;
|
|
}
|
|
continue;
|
|
}
|
|
break;
|
|
|
|
case 'D': /* Floating point rd. */
|
|
case 'S': /* Floating point rs1. */
|
|
case 'T': /* Floating point rs2. */
|
|
case 'U': /* Floating point rs1 and rs2. */
|
|
case 'R': /* Floating point rs3. */
|
|
if (reg_lookup (&s, RCLASS_FPR, ®no))
|
|
{
|
|
c = *args;
|
|
if (*s == ' ')
|
|
++s;
|
|
switch (c)
|
|
{
|
|
case 'D':
|
|
INSERT_OPERAND (RD, *ip, regno);
|
|
break;
|
|
case 'S':
|
|
INSERT_OPERAND (RS1, *ip, regno);
|
|
break;
|
|
case 'U':
|
|
INSERT_OPERAND (RS1, *ip, regno);
|
|
/* fallthru */
|
|
case 'T':
|
|
INSERT_OPERAND (RS2, *ip, regno);
|
|
break;
|
|
case 'R':
|
|
INSERT_OPERAND (RS3, *ip, regno);
|
|
break;
|
|
}
|
|
continue;
|
|
}
|
|
|
|
break;
|
|
|
|
case 'I':
|
|
my_getExpression (imm_expr, s);
|
|
if (imm_expr->X_op != O_big
|
|
&& imm_expr->X_op != O_constant)
|
|
break;
|
|
normalize_constant_expr (imm_expr);
|
|
s = expr_end;
|
|
continue;
|
|
|
|
case 'A':
|
|
my_getExpression (imm_expr, s);
|
|
normalize_constant_expr (imm_expr);
|
|
/* The 'A' format specifier must be a symbol. */
|
|
if (imm_expr->X_op != O_symbol)
|
|
break;
|
|
*imm_reloc = BFD_RELOC_32;
|
|
s = expr_end;
|
|
continue;
|
|
|
|
case 'j': /* Sign-extended immediate. */
|
|
*imm_reloc = BFD_RELOC_RISCV_LO12_I;
|
|
p = percent_op_itype;
|
|
goto alu_op;
|
|
case 'q': /* Store displacement. */
|
|
p = percent_op_stype;
|
|
*imm_reloc = BFD_RELOC_RISCV_LO12_S;
|
|
goto load_store;
|
|
case 'o': /* Load displacement. */
|
|
p = percent_op_itype;
|
|
*imm_reloc = BFD_RELOC_RISCV_LO12_I;
|
|
goto load_store;
|
|
case '0': /* AMO "displacement," which must be zero. */
|
|
p = percent_op_rtype;
|
|
*imm_reloc = BFD_RELOC_UNUSED;
|
|
load_store:
|
|
/* Check whether there is only a single bracketed expression
|
|
left. If so, it must be the base register and the
|
|
constant must be zero. */
|
|
imm_expr->X_op = O_constant;
|
|
imm_expr->X_add_number = 0;
|
|
if (*s == '(' && strchr (s + 1, '(') == 0)
|
|
continue;
|
|
alu_op:
|
|
/* If this value won't fit into a 16 bit offset, then go
|
|
find a macro that will generate the 32 bit offset
|
|
code pattern. */
|
|
if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
|
|
{
|
|
normalize_constant_expr (imm_expr);
|
|
if (imm_expr->X_op != O_constant
|
|
|| (*args == '0' && imm_expr->X_add_number != 0)
|
|
|| imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
|
|
|| imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
|
|
break;
|
|
}
|
|
|
|
s = expr_end;
|
|
continue;
|
|
|
|
case 'p': /* PC-relative offset. */
|
|
branch:
|
|
*imm_reloc = BFD_RELOC_12_PCREL;
|
|
my_getExpression (imm_expr, s);
|
|
s = expr_end;
|
|
continue;
|
|
|
|
case 'u': /* Upper 20 bits. */
|
|
p = percent_op_utype;
|
|
if (!my_getSmallExpression (imm_expr, imm_reloc, s, p)
|
|
&& imm_expr->X_op == O_constant)
|
|
{
|
|
if (imm_expr->X_add_number < 0
|
|
|| imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
|
|
as_bad (_("lui expression not in range 0..1048575"));
|
|
|
|
*imm_reloc = BFD_RELOC_RISCV_HI20;
|
|
imm_expr->X_add_number <<= RISCV_IMM_BITS;
|
|
}
|
|
s = expr_end;
|
|
continue;
|
|
|
|
case 'a': /* 20-bit PC-relative offset. */
|
|
jump:
|
|
my_getExpression (imm_expr, s);
|
|
s = expr_end;
|
|
*imm_reloc = BFD_RELOC_RISCV_JMP;
|
|
continue;
|
|
|
|
case 'c':
|
|
my_getExpression (imm_expr, s);
|
|
s = expr_end;
|
|
if (strcmp (s, "@plt") == 0)
|
|
{
|
|
*imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
|
|
s += 4;
|
|
}
|
|
else
|
|
*imm_reloc = BFD_RELOC_RISCV_CALL;
|
|
continue;
|
|
|
|
default:
|
|
as_fatal (_("internal error: bad argument type %c"), *args);
|
|
}
|
|
break;
|
|
}
|
|
s = argsStart;
|
|
error = _("illegal operands");
|
|
}
|
|
|
|
out:
|
|
/* Restore the character we might have clobbered above. */
|
|
if (save_c)
|
|
*(argsStart - 1) = save_c;
|
|
|
|
return error;
|
|
}
|
|
|
|
void
|
|
md_assemble (char *str)
|
|
{
|
|
struct riscv_cl_insn insn;
|
|
expressionS imm_expr;
|
|
bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
|
|
|
|
const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc);
|
|
|
|
if (error)
|
|
{
|
|
as_bad ("%s `%s'", error, str);
|
|
return;
|
|
}
|
|
|
|
if (insn.insn_mo->pinfo == INSN_MACRO)
|
|
macro (&insn, &imm_expr, &imm_reloc);
|
|
else
|
|
append_insn (&insn, &imm_expr, imm_reloc);
|
|
}
|
|
|
|
const char *
|
|
md_atof (int type, char *litP, int *sizeP)
|
|
{
|
|
return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
|
|
}
|
|
|
|
void
|
|
md_number_to_chars (char *buf, valueT val, int n)
|
|
{
|
|
number_to_chars_littleendian (buf, val, n);
|
|
}
|
|
|
|
const char *md_shortopts = "O::g::G:";
|
|
|
|
enum options
|
|
{
|
|
OPTION_MARCH = OPTION_MD_BASE,
|
|
OPTION_PIC,
|
|
OPTION_NO_PIC,
|
|
OPTION_MABI,
|
|
OPTION_END_OF_ENUM
|
|
};
|
|
|
|
struct option md_longopts[] =
|
|
{
|
|
{"march", required_argument, NULL, OPTION_MARCH},
|
|
{"fPIC", no_argument, NULL, OPTION_PIC},
|
|
{"fpic", no_argument, NULL, OPTION_PIC},
|
|
{"fno-pic", no_argument, NULL, OPTION_NO_PIC},
|
|
{"mabi", required_argument, NULL, OPTION_MABI},
|
|
|
|
{NULL, no_argument, NULL, 0}
|
|
};
|
|
size_t md_longopts_size = sizeof (md_longopts);
|
|
|
|
enum float_abi {
|
|
FLOAT_ABI_DEFAULT = -1,
|
|
FLOAT_ABI_SOFT,
|
|
FLOAT_ABI_SINGLE,
|
|
FLOAT_ABI_DOUBLE,
|
|
FLOAT_ABI_QUAD
|
|
};
|
|
static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
|
|
|
|
static void
|
|
riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi)
|
|
{
|
|
abi_xlen = new_xlen;
|
|
float_abi = new_float_abi;
|
|
}
|
|
|
|
int
|
|
md_parse_option (int c, const char *arg)
|
|
{
|
|
switch (c)
|
|
{
|
|
case OPTION_MARCH:
|
|
riscv_set_arch (arg);
|
|
break;
|
|
|
|
case OPTION_NO_PIC:
|
|
riscv_opts.pic = FALSE;
|
|
break;
|
|
|
|
case OPTION_PIC:
|
|
riscv_opts.pic = TRUE;
|
|
break;
|
|
|
|
case OPTION_MABI:
|
|
if (strcmp (arg, "ilp32") == 0)
|
|
riscv_set_abi (32, FLOAT_ABI_SOFT);
|
|
else if (strcmp (arg, "ilp32f") == 0)
|
|
riscv_set_abi (32, FLOAT_ABI_SINGLE);
|
|
else if (strcmp (arg, "ilp32d") == 0)
|
|
riscv_set_abi (32, FLOAT_ABI_DOUBLE);
|
|
else if (strcmp (arg, "ilp32q") == 0)
|
|
riscv_set_abi (32, FLOAT_ABI_QUAD);
|
|
else if (strcmp (arg, "lp64") == 0)
|
|
riscv_set_abi (64, FLOAT_ABI_SOFT);
|
|
else if (strcmp (arg, "lp64f") == 0)
|
|
riscv_set_abi (64, FLOAT_ABI_SINGLE);
|
|
else if (strcmp (arg, "lp64d") == 0)
|
|
riscv_set_abi (64, FLOAT_ABI_DOUBLE);
|
|
else if (strcmp (arg, "lp64q") == 0)
|
|
riscv_set_abi (64, FLOAT_ABI_QUAD);
|
|
else
|
|
return 0;
|
|
break;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
void
|
|
riscv_after_parse_args (void)
|
|
{
|
|
if (xlen == 0)
|
|
{
|
|
if (strcmp (default_arch, "riscv32") == 0)
|
|
xlen = 32;
|
|
else if (strcmp (default_arch, "riscv64") == 0)
|
|
xlen = 64;
|
|
else
|
|
as_bad ("unknown default architecture `%s'", default_arch);
|
|
}
|
|
|
|
if (riscv_subsets == NULL)
|
|
riscv_set_arch (xlen == 64 ? "rv64g" : "rv32g");
|
|
|
|
/* Add the RVC extension, regardless of -march, to support .option rvc. */
|
|
riscv_set_rvc (FALSE);
|
|
if (riscv_subset_supports ("c"))
|
|
riscv_set_rvc (TRUE);
|
|
else
|
|
riscv_add_subset ("c");
|
|
|
|
/* Infer ABI from ISA if not specified on command line. */
|
|
if (abi_xlen == 0)
|
|
abi_xlen = xlen;
|
|
else if (abi_xlen > xlen)
|
|
as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
|
|
else if (abi_xlen < xlen)
|
|
as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
|
|
|
|
if (float_abi == FLOAT_ABI_DEFAULT)
|
|
{
|
|
struct riscv_subset *subset;
|
|
|
|
/* Assume soft-float unless D extension is present. */
|
|
float_abi = FLOAT_ABI_SOFT;
|
|
|
|
for (subset = riscv_subsets; subset != NULL; subset = subset->next)
|
|
{
|
|
if (strcasecmp (subset->name, "D") == 0)
|
|
float_abi = FLOAT_ABI_DOUBLE;
|
|
if (strcasecmp (subset->name, "Q") == 0)
|
|
float_abi = FLOAT_ABI_QUAD;
|
|
}
|
|
}
|
|
|
|
/* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
|
|
elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1));
|
|
}
|
|
|
|
long
|
|
md_pcrel_from (fixS *fixP)
|
|
{
|
|
return fixP->fx_where + fixP->fx_frag->fr_address;
|
|
}
|
|
|
|
/* Apply a fixup to the object file. */
|
|
|
|
void
|
|
md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
|
|
{
|
|
unsigned int subtype;
|
|
bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
|
|
bfd_boolean relaxable = FALSE;
|
|
offsetT loc;
|
|
segT sub_segment;
|
|
|
|
/* Remember value for tc_gen_reloc. */
|
|
fixP->fx_addnumber = *valP;
|
|
|
|
switch (fixP->fx_r_type)
|
|
{
|
|
case BFD_RELOC_RISCV_HI20:
|
|
case BFD_RELOC_RISCV_LO12_I:
|
|
case BFD_RELOC_RISCV_LO12_S:
|
|
bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
|
|
| bfd_getl32 (buf), buf);
|
|
if (fixP->fx_addsy == NULL)
|
|
fixP->fx_done = TRUE;
|
|
relaxable = TRUE;
|
|
break;
|
|
|
|
case BFD_RELOC_RISCV_GOT_HI20:
|
|
case BFD_RELOC_RISCV_ADD8:
|
|
case BFD_RELOC_RISCV_ADD16:
|
|
case BFD_RELOC_RISCV_ADD32:
|
|
case BFD_RELOC_RISCV_ADD64:
|
|
case BFD_RELOC_RISCV_SUB6:
|
|
case BFD_RELOC_RISCV_SUB8:
|
|
case BFD_RELOC_RISCV_SUB16:
|
|
case BFD_RELOC_RISCV_SUB32:
|
|
case BFD_RELOC_RISCV_SUB64:
|
|
case BFD_RELOC_RISCV_RELAX:
|
|
break;
|
|
|
|
case BFD_RELOC_RISCV_TPREL_HI20:
|
|
case BFD_RELOC_RISCV_TPREL_LO12_I:
|
|
case BFD_RELOC_RISCV_TPREL_LO12_S:
|
|
case BFD_RELOC_RISCV_TPREL_ADD:
|
|
relaxable = TRUE;
|
|
/* Fall through. */
|
|
|
|
case BFD_RELOC_RISCV_TLS_GOT_HI20:
|
|
case BFD_RELOC_RISCV_TLS_GD_HI20:
|
|
case BFD_RELOC_RISCV_TLS_DTPREL32:
|
|
case BFD_RELOC_RISCV_TLS_DTPREL64:
|
|
if (fixP->fx_addsy != NULL)
|
|
S_SET_THREAD_LOCAL (fixP->fx_addsy);
|
|
else
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
|
_("TLS relocation against a constant"));
|
|
break;
|
|
|
|
case BFD_RELOC_32:
|
|
/* Use pc-relative relocation for FDE initial location.
|
|
The symbol address in .eh_frame may be adjusted in
|
|
_bfd_elf_discard_section_eh_frame, and the content of
|
|
.eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
|
|
Therefore, we cannot insert a relocation whose addend symbol is
|
|
in .eh_frame. Othrewise, the value may be adjusted twice.*/
|
|
if (fixP->fx_addsy && fixP->fx_subsy
|
|
&& (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
|
|
&& strcmp (sub_segment->name, ".eh_frame") == 0
|
|
&& S_GET_VALUE (fixP->fx_subsy)
|
|
== fixP->fx_frag->fr_address + fixP->fx_where)
|
|
{
|
|
fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
|
|
fixP->fx_subsy = NULL;
|
|
break;
|
|
}
|
|
/* Fall through. */
|
|
case BFD_RELOC_64:
|
|
case BFD_RELOC_16:
|
|
case BFD_RELOC_8:
|
|
case BFD_RELOC_RISCV_CFA:
|
|
if (fixP->fx_addsy && fixP->fx_subsy)
|
|
{
|
|
fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
|
|
fixP->fx_next->fx_addsy = fixP->fx_subsy;
|
|
fixP->fx_next->fx_subsy = NULL;
|
|
fixP->fx_next->fx_offset = 0;
|
|
fixP->fx_subsy = NULL;
|
|
|
|
switch (fixP->fx_r_type)
|
|
{
|
|
case BFD_RELOC_64:
|
|
fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
|
|
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
|
|
break;
|
|
|
|
case BFD_RELOC_32:
|
|
fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
|
|
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
|
|
break;
|
|
|
|
case BFD_RELOC_16:
|
|
fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
|
|
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
|
|
break;
|
|
|
|
case BFD_RELOC_8:
|
|
fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
|
|
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
|
|
break;
|
|
|
|
case BFD_RELOC_RISCV_CFA:
|
|
/* Load the byte to get the subtype. */
|
|
subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
|
|
loc = fixP->fx_frag->fr_fix - (subtype & 7);
|
|
switch (subtype)
|
|
{
|
|
case DW_CFA_advance_loc1:
|
|
fixP->fx_where = loc + 1;
|
|
fixP->fx_next->fx_where = loc + 1;
|
|
fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
|
|
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
|
|
break;
|
|
|
|
case DW_CFA_advance_loc2:
|
|
fixP->fx_size = 2;
|
|
fixP->fx_next->fx_size = 2;
|
|
fixP->fx_where = loc + 1;
|
|
fixP->fx_next->fx_where = loc + 1;
|
|
fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
|
|
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
|
|
break;
|
|
|
|
case DW_CFA_advance_loc4:
|
|
fixP->fx_size = 4;
|
|
fixP->fx_next->fx_size = 4;
|
|
fixP->fx_where = loc;
|
|
fixP->fx_next->fx_where = loc;
|
|
fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
|
|
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
|
|
break;
|
|
|
|
default:
|
|
if (subtype < 0x80 && (subtype & 0x40))
|
|
{
|
|
/* DW_CFA_advance_loc */
|
|
fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
|
|
fixP->fx_next->fx_frag = fixP->fx_frag;
|
|
fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
|
|
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
|
|
}
|
|
else
|
|
as_fatal (_("internal error: bad CFA value #%d"), subtype);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
/* This case is unreachable. */
|
|
abort ();
|
|
}
|
|
}
|
|
/* Fall through. */
|
|
|
|
case BFD_RELOC_RVA:
|
|
/* If we are deleting this reloc entry, we must fill in the
|
|
value now. This can happen if we have a .word which is not
|
|
resolved when it appears but is later defined. */
|
|
if (fixP->fx_addsy == NULL)
|
|
{
|
|
gas_assert (fixP->fx_size <= sizeof (valueT));
|
|
md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
|
|
fixP->fx_done = 1;
|
|
}
|
|
break;
|
|
|
|
case BFD_RELOC_RISCV_JMP:
|
|
if (fixP->fx_addsy)
|
|
{
|
|
/* Fill in a tentative value to improve objdump readability. */
|
|
bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
|
|
bfd_vma delta = target - md_pcrel_from (fixP);
|
|
bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
|
|
}
|
|
break;
|
|
|
|
case BFD_RELOC_12_PCREL:
|
|
if (fixP->fx_addsy)
|
|
{
|
|
/* Fill in a tentative value to improve objdump readability. */
|
|
bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
|
|
bfd_vma delta = target - md_pcrel_from (fixP);
|
|
bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
|
|
}
|
|
break;
|
|
|
|
case BFD_RELOC_RISCV_RVC_BRANCH:
|
|
if (fixP->fx_addsy)
|
|
{
|
|
/* Fill in a tentative value to improve objdump readability. */
|
|
bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
|
|
bfd_vma delta = target - md_pcrel_from (fixP);
|
|
bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
|
|
}
|
|
break;
|
|
|
|
case BFD_RELOC_RISCV_RVC_JUMP:
|
|
if (fixP->fx_addsy)
|
|
{
|
|
/* Fill in a tentative value to improve objdump readability. */
|
|
bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
|
|
bfd_vma delta = target - md_pcrel_from (fixP);
|
|
bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
|
|
}
|
|
break;
|
|
|
|
case BFD_RELOC_RISCV_CALL:
|
|
case BFD_RELOC_RISCV_CALL_PLT:
|
|
relaxable = TRUE;
|
|
break;
|
|
|
|
case BFD_RELOC_RISCV_PCREL_HI20:
|
|
case BFD_RELOC_RISCV_PCREL_LO12_S:
|
|
case BFD_RELOC_RISCV_PCREL_LO12_I:
|
|
relaxable = riscv_opts.relax;
|
|
break;
|
|
|
|
case BFD_RELOC_RISCV_ALIGN:
|
|
break;
|
|
|
|
default:
|
|
/* We ignore generic BFD relocations we don't know about. */
|
|
if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
|
|
as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type);
|
|
}
|
|
|
|
if (fixP->fx_subsy != NULL)
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
|
_("unsupported symbol subtraction"));
|
|
|
|
/* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
|
|
if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
|
|
{
|
|
fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
|
|
fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
|
|
fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
|
|
}
|
|
}
|
|
|
|
/* Because the value of .cfi_remember_state may changed after relaxation,
|
|
we insert a fix to relocate it again in link-time. */
|
|
|
|
void
|
|
riscv_pre_output_hook (void)
|
|
{
|
|
const frchainS *frch;
|
|
const asection *s;
|
|
|
|
for (s = stdoutput->sections; s; s = s->next)
|
|
for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
|
|
{
|
|
fragS *frag;
|
|
|
|
for (frag = frch->frch_root; frag; frag = frag->fr_next)
|
|
{
|
|
if (frag->fr_type == rs_cfa)
|
|
{
|
|
expressionS exp;
|
|
|
|
symbolS *add_symbol = frag->fr_symbol->sy_value.X_add_symbol;
|
|
symbolS *op_symbol = frag->fr_symbol->sy_value.X_op_symbol;
|
|
|
|
exp.X_op = O_subtract;
|
|
exp.X_add_symbol = add_symbol;
|
|
exp.X_add_number = 0;
|
|
exp.X_op_symbol = op_symbol;
|
|
|
|
fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
|
|
BFD_RELOC_RISCV_CFA);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/* This structure is used to hold a stack of .option values. */
|
|
|
|
struct riscv_option_stack
|
|
{
|
|
struct riscv_option_stack *next;
|
|
struct riscv_set_options options;
|
|
};
|
|
|
|
static struct riscv_option_stack *riscv_opts_stack;
|
|
|
|
/* Handle the .option pseudo-op. */
|
|
|
|
static void
|
|
s_riscv_option (int x ATTRIBUTE_UNUSED)
|
|
{
|
|
char *name = input_line_pointer, ch;
|
|
|
|
while (!is_end_of_line[(unsigned char) *input_line_pointer])
|
|
++input_line_pointer;
|
|
ch = *input_line_pointer;
|
|
*input_line_pointer = '\0';
|
|
|
|
if (strcmp (name, "rvc") == 0)
|
|
riscv_set_rvc (TRUE);
|
|
else if (strcmp (name, "norvc") == 0)
|
|
riscv_set_rvc (FALSE);
|
|
else if (strcmp (name, "pic") == 0)
|
|
riscv_opts.pic = TRUE;
|
|
else if (strcmp (name, "nopic") == 0)
|
|
riscv_opts.pic = FALSE;
|
|
else if (strcmp (name, "relax") == 0)
|
|
riscv_opts.relax = TRUE;
|
|
else if (strcmp (name, "norelax") == 0)
|
|
riscv_opts.relax = FALSE;
|
|
else if (strcmp (name, "push") == 0)
|
|
{
|
|
struct riscv_option_stack *s;
|
|
|
|
s = (struct riscv_option_stack *) xmalloc (sizeof *s);
|
|
s->next = riscv_opts_stack;
|
|
s->options = riscv_opts;
|
|
riscv_opts_stack = s;
|
|
}
|
|
else if (strcmp (name, "pop") == 0)
|
|
{
|
|
struct riscv_option_stack *s;
|
|
|
|
s = riscv_opts_stack;
|
|
if (s == NULL)
|
|
as_bad (_(".option pop with no .option push"));
|
|
else
|
|
{
|
|
riscv_opts = s->options;
|
|
riscv_opts_stack = s->next;
|
|
free (s);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_warn (_("Unrecognized .option directive: %s\n"), name);
|
|
}
|
|
*input_line_pointer = ch;
|
|
demand_empty_rest_of_line ();
|
|
}
|
|
|
|
/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
|
|
a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
|
|
use in DWARF debug information. */
|
|
|
|
static void
|
|
s_dtprel (int bytes)
|
|
{
|
|
expressionS ex;
|
|
char *p;
|
|
|
|
expression (&ex);
|
|
|
|
if (ex.X_op != O_symbol)
|
|
{
|
|
as_bad (_("Unsupported use of %s"), (bytes == 8
|
|
? ".dtpreldword"
|
|
: ".dtprelword"));
|
|
ignore_rest_of_line ();
|
|
}
|
|
|
|
p = frag_more (bytes);
|
|
md_number_to_chars (p, 0, bytes);
|
|
fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
|
|
(bytes == 8
|
|
? BFD_RELOC_RISCV_TLS_DTPREL64
|
|
: BFD_RELOC_RISCV_TLS_DTPREL32));
|
|
|
|
demand_empty_rest_of_line ();
|
|
}
|
|
|
|
/* Handle the .bss pseudo-op. */
|
|
|
|
static void
|
|
s_bss (int ignore ATTRIBUTE_UNUSED)
|
|
{
|
|
subseg_set (bss_section, 0);
|
|
demand_empty_rest_of_line ();
|
|
}
|
|
|
|
static void
|
|
riscv_make_nops (char *buf, bfd_vma bytes)
|
|
{
|
|
bfd_vma i = 0;
|
|
|
|
/* RISC-V instructions cannot begin or end on odd addresses, so this case
|
|
means we are not within a valid instruction sequence. It is thus safe
|
|
to use a zero byte, even though that is not a valid instruction. */
|
|
if (bytes % 2 == 1)
|
|
buf[i++] = 0;
|
|
|
|
/* Use at most one 2-byte NOP. */
|
|
if ((bytes - i) % 4 == 2)
|
|
{
|
|
md_number_to_chars (buf + i, RVC_NOP, 2);
|
|
i += 2;
|
|
}
|
|
|
|
/* Fill the remainder with 4-byte NOPs. */
|
|
for ( ; i < bytes; i += 4)
|
|
md_number_to_chars (buf + i, RISCV_NOP, 4);
|
|
}
|
|
|
|
/* Called from md_do_align. Used to create an alignment frag in a
|
|
code section by emitting a worst-case NOP sequence that the linker
|
|
will later relax to the correct number of NOPs. We can't compute
|
|
the correct alignment now because of other linker relaxations. */
|
|
|
|
bfd_boolean
|
|
riscv_frag_align_code (int n)
|
|
{
|
|
bfd_vma bytes = (bfd_vma) 1 << n;
|
|
bfd_vma worst_case_bytes = bytes - (riscv_opts.rvc ? 2 : 4);
|
|
char *nops = frag_more (worst_case_bytes);
|
|
expressionS ex;
|
|
|
|
/* When not relaxing, riscv_handle_align handles code alignment. */
|
|
if (!riscv_opts.relax)
|
|
return FALSE;
|
|
|
|
ex.X_op = O_constant;
|
|
ex.X_add_number = worst_case_bytes;
|
|
|
|
riscv_make_nops (nops, worst_case_bytes);
|
|
|
|
fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
|
|
&ex, FALSE, BFD_RELOC_RISCV_ALIGN);
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
/* Implement HANDLE_ALIGN. */
|
|
|
|
void
|
|
riscv_handle_align (fragS *fragP)
|
|
{
|
|
switch (fragP->fr_type)
|
|
{
|
|
case rs_align_code:
|
|
/* When relaxing, riscv_frag_align_code handles code alignment. */
|
|
if (!riscv_opts.relax)
|
|
{
|
|
bfd_signed_vma count = fragP->fr_next->fr_address
|
|
- fragP->fr_address - fragP->fr_fix;
|
|
|
|
if (count <= 0)
|
|
break;
|
|
|
|
count &= MAX_MEM_FOR_RS_ALIGN_CODE;
|
|
riscv_make_nops (fragP->fr_literal + fragP->fr_fix, count);
|
|
fragP->fr_var = count;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
int
|
|
md_estimate_size_before_relax (fragS *fragp, asection *segtype)
|
|
{
|
|
return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
|
|
}
|
|
|
|
/* Translate internal representation of relocation info to BFD target
|
|
format. */
|
|
|
|
arelent *
|
|
tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
|
|
{
|
|
arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
|
|
|
|
reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
|
|
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
|
|
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
|
|
reloc->addend = fixp->fx_addnumber;
|
|
|
|
reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
|
|
if (reloc->howto == NULL)
|
|
{
|
|
if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
|
|
&& fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
|
|
{
|
|
/* We don't have R_RISCV_8/16, but for this special case,
|
|
we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
|
|
return reloc;
|
|
}
|
|
|
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
|
_("cannot represent %s relocation in object file"),
|
|
bfd_get_reloc_code_name (fixp->fx_r_type));
|
|
return NULL;
|
|
}
|
|
|
|
return reloc;
|
|
}
|
|
|
|
int
|
|
riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
|
|
{
|
|
if (RELAX_BRANCH_P (fragp->fr_subtype))
|
|
{
|
|
offsetT old_var = fragp->fr_var;
|
|
fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
|
|
return fragp->fr_var - old_var;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Expand far branches to multi-instruction sequences. */
|
|
|
|
static void
|
|
md_convert_frag_branch (fragS *fragp)
|
|
{
|
|
bfd_byte *buf;
|
|
expressionS exp;
|
|
fixS *fixp;
|
|
insn_t insn;
|
|
int rs1, reloc;
|
|
|
|
buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
|
|
|
|
exp.X_op = O_symbol;
|
|
exp.X_add_symbol = fragp->fr_symbol;
|
|
exp.X_add_number = fragp->fr_offset;
|
|
|
|
gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
|
|
|
|
if (RELAX_BRANCH_RVC (fragp->fr_subtype))
|
|
{
|
|
switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
|
|
{
|
|
case 8:
|
|
case 4:
|
|
/* Expand the RVC branch into a RISC-V one. */
|
|
insn = bfd_getl16 (buf);
|
|
rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
|
|
if ((insn & MASK_C_J) == MATCH_C_J)
|
|
insn = MATCH_JAL;
|
|
else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
|
|
insn = MATCH_JAL | (X_RA << OP_SH_RD);
|
|
else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
|
|
insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
|
|
else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
|
|
insn = MATCH_BNE | (rs1 << OP_SH_RS1);
|
|
else
|
|
abort ();
|
|
bfd_putl32 (insn, buf);
|
|
break;
|
|
|
|
case 6:
|
|
/* Invert the branch condition. Branch over the jump. */
|
|
insn = bfd_getl16 (buf);
|
|
insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
|
|
insn |= ENCODE_RVC_B_IMM (6);
|
|
bfd_putl16 (insn, buf);
|
|
buf += 2;
|
|
goto jump;
|
|
|
|
case 2:
|
|
/* Just keep the RVC branch. */
|
|
reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
|
|
? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
|
|
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
|
|
2, &exp, FALSE, reloc);
|
|
buf += 2;
|
|
goto done;
|
|
|
|
default:
|
|
abort ();
|
|
}
|
|
}
|
|
|
|
switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
|
|
{
|
|
case 8:
|
|
gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
|
|
|
|
/* Invert the branch condition. Branch over the jump. */
|
|
insn = bfd_getl32 (buf);
|
|
insn ^= MATCH_BEQ ^ MATCH_BNE;
|
|
insn |= ENCODE_SBTYPE_IMM (8);
|
|
md_number_to_chars ((char *) buf, insn, 4);
|
|
buf += 4;
|
|
|
|
jump:
|
|
/* Jump to the target. */
|
|
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
|
|
4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
|
|
md_number_to_chars ((char *) buf, MATCH_JAL, 4);
|
|
buf += 4;
|
|
break;
|
|
|
|
case 4:
|
|
reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
|
|
? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
|
|
fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
|
|
4, &exp, FALSE, reloc);
|
|
buf += 4;
|
|
break;
|
|
|
|
default:
|
|
abort ();
|
|
}
|
|
|
|
done:
|
|
fixp->fx_file = fragp->fr_file;
|
|
fixp->fx_line = fragp->fr_line;
|
|
|
|
gas_assert (buf == (bfd_byte *)fragp->fr_literal
|
|
+ fragp->fr_fix + fragp->fr_var);
|
|
|
|
fragp->fr_fix += fragp->fr_var;
|
|
}
|
|
|
|
/* Relax a machine dependent frag. This returns the amount by which
|
|
the current size of the frag should change. */
|
|
|
|
void
|
|
md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
|
|
fragS *fragp)
|
|
{
|
|
gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
|
|
md_convert_frag_branch (fragp);
|
|
}
|
|
|
|
void
|
|
md_show_usage (FILE *stream)
|
|
{
|
|
fprintf (stream, _("\
|
|
RISC-V options:\n\
|
|
-fpic generate position-independent code\n\
|
|
-fno-pic don't generate position-independent code (default)\n\
|
|
-march=ISA set the RISC-V architecture\n\
|
|
-mabi=ABI set the RISC-V ABI\n\
|
|
"));
|
|
}
|
|
|
|
/* Standard calling conventions leave the CFA at SP on entry. */
|
|
void
|
|
riscv_cfi_frame_initial_instructions (void)
|
|
{
|
|
cfi_add_CFA_def_cfa_register (X_SP);
|
|
}
|
|
|
|
int
|
|
tc_riscv_regname_to_dw2regnum (char *regname)
|
|
{
|
|
int reg;
|
|
|
|
if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
|
|
return reg;
|
|
|
|
if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
|
|
return reg + 32;
|
|
|
|
as_bad (_("unknown register `%s'"), regname);
|
|
return -1;
|
|
}
|
|
|
|
void
|
|
riscv_elf_final_processing (void)
|
|
{
|
|
elf_elfheader (stdoutput)->e_flags |= elf_flags;
|
|
}
|
|
|
|
/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
|
|
since these directives break relaxation when used with symbol deltas. */
|
|
|
|
static void
|
|
s_riscv_leb128 (int sign)
|
|
{
|
|
expressionS exp;
|
|
char *save_in = input_line_pointer;
|
|
|
|
expression (&exp);
|
|
if (exp.X_op != O_constant)
|
|
as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
|
|
demand_empty_rest_of_line ();
|
|
|
|
input_line_pointer = save_in;
|
|
return s_leb128 (sign);
|
|
}
|
|
|
|
/* Pseudo-op table. */
|
|
|
|
static const pseudo_typeS riscv_pseudo_table[] =
|
|
{
|
|
/* RISC-V-specific pseudo-ops. */
|
|
{"option", s_riscv_option, 0},
|
|
{"half", cons, 2},
|
|
{"word", cons, 4},
|
|
{"dword", cons, 8},
|
|
{"dtprelword", s_dtprel, 4},
|
|
{"dtpreldword", s_dtprel, 8},
|
|
{"bss", s_bss, 0},
|
|
{"uleb128", s_riscv_leb128, 0},
|
|
{"sleb128", s_riscv_leb128, 1},
|
|
|
|
{ NULL, NULL, 0 },
|
|
};
|
|
|
|
void
|
|
riscv_pop_insert (void)
|
|
{
|
|
extern void pop_insert (const pseudo_typeS *);
|
|
|
|
pop_insert (riscv_pseudo_table);
|
|
}
|