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binutils-gdb/gdb/riscv-tdep.h
Andrew Burgess 113b7b8142 gdb/riscv: Split ISA and ABI features
The goal of this commit is to allow RV64 binaries compiled for the 'F'
extension to run on a target that supports both the 'F' and 'D'
extensions.

The 'D' extension depends on the 'F' extension and chapter 9 of the
RISC-V ISA manual implies that running a program compiled for 'F' on
a 'D' target should be fine.

To support this the gdbarch now holds two feature sets, one represents
the features that are present on the target, and one represents the
features requested in the ELF flags.

The existing error checks are relaxed slightly to allow binaries
compiled for 32-bit 'F' extension to run on targets with the 64-bit
'D' extension.

A new set of functions called riscv_abi_{xlen,flen} are added to
compliment the existing riscv_isa_{xlen,flen}, and some callers to the
isa functions now call the abi functions when that is appropriate.

In riscv_call_arg_struct two asserts are removed, these asserts no
longer make sense.  The asserts were both like this:

    gdb_assert (TYPE_LENGTH (ainfo->type)
                <= (cinfo->flen + cinfo->xlen));

And were made in two cases, when passing structures like these:

   struct {
     integer field1;
     float   field2;
   };

or,

   struct {
     float   field1;
     integer field2;
   };

When running on an RV64 target which only has 32-bit float then the
integer field could be 64-bits, while if the float field is 32-bits
the overall size of the structure can be 128-bits (with 32-bits of
padding).  In this case the assertion would fail, however, the code
isn't incorrect, so its safe to just remove the assertion.

This was tested by running on an RV64IMFDC target using a compiler
configured for RV64IMFC, and comparing the results with those obtained
when using a compiler configured for RV64IMFDC.  The only regressions
I see (now) are in gdb.base/store.exp and are related too different
code generation choices GCC makes between the two targets.

Finally, this commit does not make any attempt to support running
binaries compiled for RV32 on an RV64 target, though nothing in here
should prevent that being supported in the future.

gdb/ChangeLog:

	* arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>:
	Delete.
	<operator==>: Update with for removed field.
	<hash>: Likewise.
	* riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to...
	<isa_features>: ...this.
	<abi_features>: New field.
	(riscv_isa_flen): Update comment.
	(riscv_abi_xlen): New declaration.
	(riscv_abi_flen): New declaration.
	* riscv-tdep.c (riscv_isa_xlen): Update to get answer from
	isa_features.
	(riscv_abi_xlen): New function.
	(riscv_isa_flen): Update to get answer from isa_features.
	(riscv_abi_flen): New function.
	(riscv_has_fp_abi): Update to get answer from abi_features.
	(riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa
	xlen and flen.
	(riscv_call_info) <xlen, flen>: Update comment.
	(riscv_call_arg_struct): Remove invalid assertions
	(riscv_features_from_gdbarch_info): Update now hw_float_abi field
	is removed.
	(riscv_gdbarch_init): Gather isa features and abi features
	separately, ensure both match on the gdbarch when reusing an old
	gdbarch.  Relax an error check to allow 32-bit abi float to run on
	a target with 64-bit float hardware.
2019-01-01 22:56:16 +00:00

119 lines
4.4 KiB
C++

/* Target-dependent header for the RISC-V architecture, for GDB, the
GNU Debugger.
Copyright (C) 2018-2019 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef RISCV_TDEP_H
#define RISCV_TDEP_H
#include "arch/riscv.h"
/* RiscV register numbers. */
enum
{
RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */
RISCV_RA_REGNUM = 1, /* Return Address. */
RISCV_SP_REGNUM = 2, /* Stack Pointer. */
RISCV_GP_REGNUM = 3, /* Global Pointer. */
RISCV_TP_REGNUM = 4, /* Thread Pointer. */
RISCV_FP_REGNUM = 8, /* Frame Pointer. */
RISCV_A0_REGNUM = 10, /* First argument. */
RISCV_A1_REGNUM = 11, /* Second argument. */
RISCV_PC_REGNUM = 32, /* Program Counter. */
RISCV_NUM_INTEGER_REGS = 32,
RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */
RISCV_FA0_REGNUM = 43,
RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
#define DECLARE_CSR(name, num) \
RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
RISCV_LAST_CSR_REGNUM = 4160,
RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
RISCV_PRIV_REGNUM = 4161,
RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
};
/* RiscV DWARF register numbers. */
enum
{
RISCV_DWARF_REGNUM_X0 = 0,
RISCV_DWARF_REGNUM_X31 = 31,
RISCV_DWARF_REGNUM_F0 = 32,
RISCV_DWARF_REGNUM_F31 = 63,
};
/* RISC-V specific per-architecture information. */
struct gdbarch_tdep
{
/* Features about the target hardware that impact how the gdbarch is
configured. Two gdbarch instances are compatible only if this field
matches. */
struct riscv_gdbarch_features isa_features;
/* Features about the abi that impact how the gdbarch is configured. Two
gdbarch instances are compatible only if this field matches. */
struct riscv_gdbarch_features abi_features;
/* ISA-specific data types. */
struct type *riscv_fpreg_d_type = nullptr;
};
/* Return the width in bytes of the general purpose registers for GDBARCH.
Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
RV128. */
extern int riscv_isa_xlen (struct gdbarch *gdbarch);
/* Return the width in bytes of the hardware floating point registers for
GDBARCH. If this architecture has no floating point registers, then
return 0. Possible values are 4, 8, or 16 for depending on which of
single, double or quad floating point support is available. */
extern int riscv_isa_flen (struct gdbarch *gdbarch);
/* Return the width in bytes of the general purpose register abi for
GDBARCH. This can be equal to, or less than RISCV_ISA_XLEN and reflects
how the binary was compiled rather than the hardware that is available.
It is possible that a binary compiled for RV32 is being run on an RV64
target, in which case the isa xlen is 8-bytes, and the abi xlen is
4-bytes. This will impact how inferior functions are called. */
extern int riscv_abi_xlen (struct gdbarch *gdbarch);
/* Return the width in bytes of the floating point register abi for
GDBARCH. This reflects how the binary was compiled rather than the
hardware that is available. It is possible that a binary is compiled
for single precision floating point, and then run on a target with
double precision floating point. A return value of 0 indicates that no
floating point abi is in use (floating point arguments will be passed
in integer registers) other possible return value are 4, 8, or 16 as
with RISCV_ISA_FLEN. */
extern int riscv_abi_flen (struct gdbarch *gdbarch);
/* Single step based on where the current instruction will take us. */
extern std::vector<CORE_ADDR> riscv_software_single_step
(struct regcache *regcache);
#endif /* RISCV_TDEP_H */