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886a250647
bfd * archures.c: Remove support for older ARC. Added support for new ARC cpus (ARC600, ARC601, ARC700, ARCV2). * bfd-in2.h: Likewise. * config.bfd: Likewise. * cpu-arc.c: Likewise. * elf32-arc.c: Totally changed file with a refactored inplementation of the ARC port. * libbfd.h: Added ARC specific relocation types. * reloc.c: Likewise. gas * config/tc-arc.c: Revamped file for ARC support. * config/tc-arc.h: Likewise. * doc/as.texinfo: Add new ARC options. * doc/c-arc.texi: Likewise. ld * configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*. * emulparams/arcebelf_prof.sh: New file * emulparams/arcebelf.sh: Likewise. * emulparams/arceblinux_prof.sh: Likewise. * emulparams/arceblinux.sh: Likewise. * emulparams/arcelf_prof.sh: Likewise. * emulparams/arcelf.sh: Likewise. * emulparams/arclinux_prof.sh: Likewise. * emulparams/arclinux.sh: Likewise. * emulparams/arcv2elfx.sh: Likewise. * emulparams/arcv2elf.sh: Likewise. * emultempl/arclinux.em: Likewise. * scripttempl/arclinux.sc: Likewise. * scripttempl/elfarc.sc: Likewise. * scripttempl/elfarcv2.sc: Likewise * Makefile.am: Add new ARC emulations. * Makefile.in: Regenerate. * NEWS: Mention the new feature. opcodes * arc-dis.c: Revamped file for ARC support * arc-dis.h: Likewise. * arc-ext.c: Likewise. * arc-ext.h: Likewise. * arc-opc.c: Likewise. * arc-fxi.h: New file. * arc-regs.h: Likewise. * arc-tbl.h: Likewise. binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact and ARCv2. (get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT. (guess_is_rela): Likewise. (dump_relocations): Likewise. (is_32bit_abs_reloc): Likewise. (is_16bit_abs_reloc): Likewise. (is_none_reloc): Likewise. * NEWS: Mention the new feature. include * dis-asm.h (arc_get_disassembler): Correct declaration. * arc-reloc.def: Macro file with definition of all relocation types. * arc.h: Changed macros for the newly supported ARC cpus. Altered enum defining the supported relocations. * common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added macro for EM_ARC_COMPACT2. * arc-func.h: New file. * arc.h: Likewise.
500 lines
12 KiB
C
500 lines
12 KiB
C
/* ARC target-dependent stuff. Extension structure access functions
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Copyright (C) 1995-2015 Free Software Foundation, Inc.
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include "bfd.h"
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#include "arc-ext.h"
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#include "elf/arc.h"
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#include "libiberty.h"
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/* This module provides support for extensions to the ARC processor
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architecture. */
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/* Local constants. */
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#define FIRST_EXTENSION_CORE_REGISTER 32
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#define LAST_EXTENSION_CORE_REGISTER 59
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#define FIRST_EXTENSION_CONDITION_CODE 0x10
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#define LAST_EXTENSION_CONDITION_CODE 0x1f
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#define NUM_EXT_CORE \
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(LAST_EXTENSION_CORE_REGISTER - FIRST_EXTENSION_CORE_REGISTER + 1)
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#define NUM_EXT_COND \
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(LAST_EXTENSION_CONDITION_CODE - FIRST_EXTENSION_CONDITION_CODE + 1)
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#define INST_HASH_BITS 6
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#define INST_HASH_SIZE (1 << INST_HASH_BITS)
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#define INST_HASH_MASK (INST_HASH_SIZE - 1)
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/* Local types. */
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/* These types define the information stored in the table. */
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struct ExtInstruction
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{
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char major;
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char minor;
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char flags;
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char* name;
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struct ExtInstruction* next;
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};
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struct ExtAuxRegister
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{
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long address;
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char* name;
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struct ExtAuxRegister* next;
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};
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struct ExtCoreRegister
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{
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short number;
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enum ExtReadWrite rw;
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char* name;
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};
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struct arcExtMap
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{
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struct ExtAuxRegister* auxRegisters;
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struct ExtInstruction* instructions[INST_HASH_SIZE];
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struct ExtCoreRegister coreRegisters[NUM_EXT_CORE];
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char* condCodes[NUM_EXT_COND];
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};
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/* Local data. */
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/* Extension table. */
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static struct arcExtMap arc_extension_map;
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/* Local macros. */
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/* A hash function used to map instructions into the table. */
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#define INST_HASH(MAJOR, MINOR) ((((MAJOR) << 3) ^ (MINOR)) & INST_HASH_MASK)
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/* Local functions. */
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static void
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create_map (unsigned char *block,
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unsigned long length)
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{
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unsigned char *p = block;
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while (p && p < (block + length))
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{
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/* p[0] == length of record
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p[1] == type of record
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For instructions:
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p[2] = opcode
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p[3] = minor opcode (if opcode == 3)
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p[4] = flags
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p[5]+ = name
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For core regs and condition codes:
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p[2] = value
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p[3]+ = name
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For auxiliary regs:
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p[2..5] = value
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p[6]+ = name
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(value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]). */
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/* The sequence of records is temrinated by an "empty"
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record. */
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if (p[0] == 0)
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break;
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switch (p[1])
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{
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case EXT_INSTRUCTION:
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{
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struct ExtInstruction *insn = XNEW (struct ExtInstruction);
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int major = p[2];
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int minor = p[3];
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struct ExtInstruction **bucket =
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&arc_extension_map.instructions[INST_HASH (major, minor)];
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insn->name = xstrdup ((char *) (p + 5));
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insn->major = major;
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insn->minor = minor;
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insn->flags = p[4];
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insn->next = *bucket;
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*bucket = insn;
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break;
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}
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case EXT_CORE_REGISTER:
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{
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unsigned char number = p[2];
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char* name = (char *) (p + 3);
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arc_extension_map.
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coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].number
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= number;
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arc_extension_map.
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coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].rw
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= REG_READWRITE;
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arc_extension_map.
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coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name
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= xstrdup (name);
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break;
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}
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case EXT_LONG_CORE_REGISTER:
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{
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unsigned char number = p[2];
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char* name = (char *) (p + 7);
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enum ExtReadWrite rw = p[6];
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arc_extension_map.
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coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].number
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= number;
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arc_extension_map.
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coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].rw
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= rw;
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arc_extension_map.
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coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name
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= xstrdup (name);
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}
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case EXT_COND_CODE:
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{
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char *cc_name = xstrdup ((char *) (p + 3));
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arc_extension_map.
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condCodes[p[2] - FIRST_EXTENSION_CONDITION_CODE]
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= cc_name;
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break;
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}
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case EXT_AUX_REGISTER:
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{
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/* Trickier -- need to store linked list of these. */
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struct ExtAuxRegister *newAuxRegister
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= XNEW (struct ExtAuxRegister);
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char *aux_name = xstrdup ((char *) (p + 6));
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newAuxRegister->name = aux_name;
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newAuxRegister->address = (p[2] << 24) | (p[3] << 16)
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| (p[4] << 8) | p[5];
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newAuxRegister->next = arc_extension_map.auxRegisters;
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arc_extension_map.auxRegisters = newAuxRegister;
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break;
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}
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default:
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break;
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}
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p += p[0]; /* Move on to next record. */
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}
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}
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/* Free memory that has been allocated for the extensions. */
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static void
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destroy_map (void)
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{
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struct ExtAuxRegister *r;
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unsigned int i;
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/* Free auxiliary registers. */
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r = arc_extension_map.auxRegisters;
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while (r)
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{
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/* N.B. after r has been freed, r->next is invalid! */
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struct ExtAuxRegister* next = r->next;
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free (r->name);
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free (r);
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r = next;
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}
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/* Free instructions. */
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for (i = 0; i < INST_HASH_SIZE; i++)
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{
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struct ExtInstruction *insn = arc_extension_map.instructions[i];
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while (insn)
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{
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/* N.B. after insn has been freed, insn->next is invalid! */
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struct ExtInstruction *next = insn->next;
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free (insn->name);
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free (insn);
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insn = next;
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}
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}
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/* Free core registers. */
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for (i = 0; i < NUM_EXT_CORE; i++)
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{
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if (arc_extension_map.coreRegisters[i].name)
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free (arc_extension_map.coreRegisters[i].name);
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}
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/* Free condition codes. */
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for (i = 0; i < NUM_EXT_COND; i++)
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{
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if (arc_extension_map.condCodes[i])
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free (arc_extension_map.condCodes[i]);
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}
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memset (&arc_extension_map, 0, sizeof (arc_extension_map));
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}
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static const char *
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ExtReadWrite_image (enum ExtReadWrite val)
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{
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switch (val)
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{
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case REG_INVALID : return "INVALID";
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case REG_READ : return "RO";
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case REG_WRITE : return "WO";
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case REG_READWRITE: return "R/W";
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default : return "???";
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}
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}
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/* Externally visible functions. */
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/* Get the name of an extension instruction. */
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const char *
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arcExtMap_instName (int opcode,
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int insn,
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int *flags)
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{
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/* Here the following tasks need to be done. First of all, the
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opcode stored in the Extension Map is the real opcode. However,
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the subopcode stored in the instruction to be disassembled is
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mangled. We pass (in minor opcode), the instruction word. Here
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we will un-mangle it and get the real subopcode which we can look
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for in the Extension Map. This function is used both for the
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ARCTangent and the ARCompact, so we would also need some sort of
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a way to distinguish between the two architectures. This is
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because the ARCTangent does not do any of this mangling so we
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have no issues there. */
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/* If P[22:23] is 0 or 2 then un-mangle using iiiiiI. If it is 1
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then use iiiiIi. Now, if P is 3 then check M[5:5] and if it is 0
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then un-mangle using iiiiiI else iiiiii. */
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unsigned char minor;
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struct ExtInstruction *temp;
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/* 16-bit instructions. */
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if (0x08 <= opcode && opcode <= 0x0b)
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{
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unsigned char b, c, i;
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b = (insn & 0x0700) >> 8;
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c = (insn & 0x00e0) >> 5;
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i = (insn & 0x001f);
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if (i)
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minor = i;
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else
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minor = (c == 0x07) ? b : c;
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}
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/* 32-bit instructions. */
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else
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{
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unsigned char I, A, B;
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I = (insn & 0x003f0000) >> 16;
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A = (insn & 0x0000003f);
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B = ((insn & 0x07000000) >> 24) | ((insn & 0x00007000) >> 9);
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if (I != 0x2f)
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{
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#ifndef UNMANGLED
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switch (P)
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{
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case 3:
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if (M)
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{
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minor = I;
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break;
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}
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case 0:
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case 2:
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minor = (I >> 1) | ((I & 0x1) << 5);
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break;
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case 1:
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minor = (I >> 1) | (I & 0x1) | ((I & 0x2) << 4);
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}
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#else
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minor = I;
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#endif
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}
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else
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{
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if (A != 0x3f)
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minor = A;
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else
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minor = B;
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}
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}
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temp = arc_extension_map.instructions[INST_HASH (opcode, minor)];
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while (temp)
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{
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if ((temp->major == opcode) && (temp->minor == minor))
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{
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*flags = temp->flags;
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return temp->name;
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}
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temp = temp->next;
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}
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return NULL;
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}
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/* Get the name of an extension core register. */
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const char *
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arcExtMap_coreRegName (int regnum)
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{
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if (regnum < FIRST_EXTENSION_CORE_REGISTER
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|| regnum > LAST_EXTENSION_CONDITION_CODE)
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return NULL;
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return arc_extension_map.
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coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name;
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}
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/* Get the access mode of an extension core register. */
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enum ExtReadWrite
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arcExtMap_coreReadWrite (int regnum)
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{
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if (regnum < FIRST_EXTENSION_CORE_REGISTER
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|| regnum > LAST_EXTENSION_CONDITION_CODE)
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return REG_INVALID;
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return arc_extension_map.
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coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw;
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}
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/* Get the name of an extension condition code. */
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const char *
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arcExtMap_condCodeName (int code)
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{
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if (code < FIRST_EXTENSION_CONDITION_CODE
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|| code > LAST_EXTENSION_CONDITION_CODE)
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return NULL;
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return arc_extension_map.
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condCodes[code - FIRST_EXTENSION_CONDITION_CODE];
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}
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/* Get the name of an extension auxiliary register. */
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const char *
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arcExtMap_auxRegName (long address)
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{
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/* Walk the list of auxiliary register names and find the name. */
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struct ExtAuxRegister *r;
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for (r = arc_extension_map.auxRegisters; r; r = r->next)
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{
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if (r->address == address)
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return (const char *)r->name;
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}
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return NULL;
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}
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/* Load extensions described in .arcextmap and
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.gnu.linkonce.arcextmap.* ELF section. */
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void
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build_ARC_extmap (bfd *text_bfd)
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{
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asection *sect;
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/* The map is built each time gdb loads an executable file - so free
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any existing map, as the map defined by the new file may differ
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from the old. */
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destroy_map ();
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for (sect = text_bfd->sections; sect != NULL; sect = sect->next)
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if (!strncmp (sect->name,
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".gnu.linkonce.arcextmap.",
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sizeof (".gnu.linkonce.arcextmap.") - 1)
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|| !strcmp (sect->name,".arcextmap"))
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{
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bfd_size_type count = bfd_get_section_size (sect);
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unsigned char* buffer = xmalloc (count);
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if (buffer)
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{
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if (bfd_get_section_contents (text_bfd, sect, buffer, 0, count))
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create_map (buffer, count);
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free (buffer);
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}
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}
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}
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void
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dump_ARC_extmap (void)
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{
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struct ExtAuxRegister *r;
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int i;
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r = arc_extension_map.auxRegisters;
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while (r)
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{
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printf ("AUX : %s %ld\n", r->name, r->address);
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r = r->next;
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}
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for (i = 0; i < INST_HASH_SIZE; i++)
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{
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struct ExtInstruction *insn;
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for (insn = arc_extension_map.instructions[i];
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insn != NULL; insn = insn->next)
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printf ("INST: %d %d %x %s\n", insn->major, insn->minor,
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insn->flags, insn->name);
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}
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for (i = 0; i < NUM_EXT_CORE; i++)
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{
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struct ExtCoreRegister reg = arc_extension_map.coreRegisters[i];
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if (reg.name)
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printf ("CORE: %s %d %s\n", reg.name, reg.number,
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ExtReadWrite_image (reg.rw));
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}
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for (i = 0; i < NUM_EXT_COND; i++)
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if (arc_extension_map.condCodes[i])
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printf ("COND: %s\n", arc_extension_map.condCodes[i]);
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}
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