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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
118 lines
2.5 KiB
ArmAsm
118 lines
2.5 KiB
ArmAsm
# Hitachi H8 testcase 'inc, inc.w, inc.l'
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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start
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inc_b:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; inc.b Rd
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inc.b r0h ; Increment 8-bit reg by one
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa6a5 r0 ; inc result: a6|a5
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a6a5 er0 ; inc result: a5|a5|a6|a5
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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inc_w_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; inc.w #1, Rd
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inc.w #1, r0 ; Increment 16-bit reg by one
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa5a6 r0 ; inc result: a5|a6
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test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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inc_w_2:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; inc.w #2, Rd
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inc.w #2, r0 ; Increment 16-bit reg by two
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa5a7 r0 ; inc result: a5|a7
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test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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inc_l_1:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; inc.l #1, eRd
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inc.l #1, er0 ; Increment 32-bit reg by one
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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inc_l_2:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; inc.l #2, eRd
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inc.l #2, er0 ; Increment 32-bit reg by two
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.endif
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pass
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exit 0
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