mirror of
https://sourceware.org/git/binutils-gdb.git
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9d7c4ba5e5
* addb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg>.
* andb.s: Likewise.
* cmpb.s: Likewise.
* orb.s: Likewise.
* subb.s: Likewise.
* xorb.s: Likewise.
* movb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg>
@reg+,@reg+ / @-reg,@-reg.
* movw.s: Likewise.
* movl.s: Likewise.
576 lines
12 KiB
ArmAsm
576 lines
12 KiB
ArmAsm
# Hitachi H8 testcase 'and.b'
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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# Instructions tested:
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# and.b #xx:8, rd ; e rd xxxxxxxx
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# and.b #xx:8, @erd ; 7 d rd ???? e ???? xxxxxxxx
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# and.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx
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# and.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx
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# and.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx
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# and.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx
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# and.b rs, rd ; 1 6 rs rd
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# and.b reg8, @erd ; 7 d rd ???? 1 6 rs ????
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# and.b reg8, @erd+ ; 0 1 7 9 8 rd 6 rs
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# and.b reg8, @erd- ; 0 1 7 9 a rd 6 rs
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# and.b reg8, @+erd ; 0 1 7 9 9 rd 6 rs
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# and.b reg8, @-erd ; 0 1 7 9 b rd 6 rs
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#
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# andc #xx:8, ccr ; 0 6 xxxxxxxx
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# andc #xx:8, exr ; 0 1 4 1 0 6 xxxxxxxx
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# Coming soon:
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# ...
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.data
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pre_byte: .byte 0
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byte_dest: .byte 0xa5
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post_byte: .byte 0
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start
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and_b_imm8_reg8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; and.b #xx:8,Rd
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and.b #0xaa, r0l ; Immediate 8-bit operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa5a0 r0 ; and result: a5 & aa
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a5a0 er0 ; and result: a5 & aa
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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and_b_imm8_rdind:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; and.b #xx:8,@eRd
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mov #byte_dest, er0
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and.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst
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;;; .word 0x7d00
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;;; .word 0xe0aa
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest, er0 ; er0 still contains address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the and to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xa0, r0l
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beq .L1
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fail
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.L1:
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and_b_imm8_rdpostinc:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; and.b #xx:8,@eRd+
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mov #byte_dest, er0
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and.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
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;;; .word 0x0174
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;;; .word 0x6c08
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;;; .word 0xe055
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 post_byte, er0 ; er0 contains address plus one
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the and to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0x05, r0l
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beq .L2
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fail
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.L2:
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;; special case same register
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mov.l #byte_dest, er0
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mov.b @er0, r1h
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mov.b r0l, r1l
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and.b r0l, @er0+
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inc.b r1l
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and.b r1h, r1l
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mov.b @byte_dest, r0l
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cmp.b r1l, r0l
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beq .L22
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fail
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.L22:
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and_b_imm8_rdpostdec:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; and.b #xx:8,@eRd-
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mov #byte_dest, er0
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and.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest
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;;; .word 0x0176
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;;; .word 0x6c08
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;;; .word 0xe0aa
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 pre_byte, er0 ; er0 contains address minus one
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the and to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xa0, r0l
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beq .L3
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fail
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.L3:
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;; special case same register
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mov.l #byte_dest, er0
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mov.b @er0, r1h
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mov.b r0l, r1l
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and.b r0l, @er0-
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dec.b r1l
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and.b r1h, r1l
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mov.b @byte_dest, r0l
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cmp.b r1l, r0l
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beq .L23
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fail
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.L23:
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and_b_imm8_rdpreinc:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; and.b #xx:8,@+eRd
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mov #pre_byte, er0
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and.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest
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;;; .word 0x0175
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;;; .word 0x6c08
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;;; .word 0xe055
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 byte_dest, er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the and to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0x05, r0l
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beq .L4
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fail
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.L4:
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;; special case same register
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mov.l #pre_byte, er0
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mov.b @byte_dest, r1h
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mov.b r0l, r1l
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and.b r0l, @+er0
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inc.b r1l
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and.b r1h, r1l
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mov.b @byte_dest, r0l
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cmp.b r1l, r0l
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beq .L24
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fail
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.L24:
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and_b_imm8_rdpredec:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; and.b #xx:8,@-eRd
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mov #post_byte, er0
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and.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest
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;;; .word 0x0177
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;;; .word 0x6c08
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;;; .word 0xe0aa
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest, er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the and to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xa0, r0l
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beq .L5
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fail
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.L5:
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;; special case same register
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mov.l #post_byte, er0
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mov.b @byte_dest, r1h
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mov.b r0l, r1l
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and.b r0l, @-er0
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dec.b r1l
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and.b r1h, r1l
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mov.b @byte_dest, r0l
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cmp.b r1l, r0l
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beq .L25
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fail
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.L25:
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.endif ; h8sx
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and_b_reg8_reg8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; and.b Rs,Rd
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mov.b #0xaa, r0h
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and.b r0h, r0l ; Register operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xaaa0 r0 ; and result: a5 & aa
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5aaa0 er0 ; and result: a5 & aa
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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and_b_reg8_rdind:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; and.b rs8,@eRd ; And to register indirect
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mov #byte_dest, er0
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mov #0x55, r1l
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and.b r1l, @er0 ; reg8 src, reg indirect dest
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;;; .word 0x7d00
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;;; .word 0x1690
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 byte_dest er0 ; er0 still contains address
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test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the and to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0x05, r0l
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beq .L6
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fail
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.L6:
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and_b_reg8_rdpostinc:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; and.b rs8,@eRd+ ; And to register post-incr
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mov #byte_dest, er0
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mov #0xaa, r1l
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and.b r1l, @er0+ ; reg8 src, reg post-incr dest
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;;; .word 0x0179
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;;; .word 0x8069
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 post_byte er0 ; er0 contains address plus one
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test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the and to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xa0, r0l
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beq .L7
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fail
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.L7:
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and_b_reg8_rdpostdec:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; and.b rs8,@eRd- ; And to register post-decr
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mov #byte_dest, er0
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mov #0x55, r1l
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and.b r1l, @er0- ; reg8 src, reg post-decr dest
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;;; .word 0x0179
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;;; .word 0xa069
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 pre_byte er0 ; er0 contains address minus one
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test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the and to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0x05, r0l
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beq .L8
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fail
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.L8:
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and_b_reg8_rdpreinc:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; and.b rs8,@+eRd ; And to register post-incr
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mov #pre_byte, er0
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mov #0xaa, r1l
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and.b r1l, @+er0 ; reg8 src, reg post-incr dest
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;;; .word 0x0179
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;;; .word 0x9069
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the and to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xa0, r0l
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beq .L9
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fail
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.L9:
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and_b_reg8_rdpredec:
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mov #byte_dest, er0
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mov.b #0xa5, r1l
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mov.b r1l, @er0
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; and.b rs8,@-eRd ; And to register post-decr
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mov #post_byte, er0
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mov #0x55, r1l
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and.b r1l, @-er0 ; reg8 src, reg post-decr dest
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;;; .word 0x0179
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|
;;; .word 0xb069
|
|
|
|
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_clear
|
|
|
|
test_h_gr32 byte_dest er0 ; er0 contains destination address
|
|
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
|
|
|
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
;; Now check the result of the and to memory.
|
|
sub.b r0l, r0l
|
|
mov.b @byte_dest, r0l
|
|
cmp.b #0x05, r0l
|
|
beq .L10
|
|
fail
|
|
.L10:
|
|
.endif ; h8sx
|
|
|
|
andc_imm8_ccr:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; andc #xx:8,ccr
|
|
set_ccr 0xff
|
|
|
|
test_neg_set
|
|
andc #0xf7, ccr ; Immediate 8-bit operand (neg flag)
|
|
test_neg_clear
|
|
|
|
test_zero_set
|
|
andc #0xfb, ccr ; Immediate 8-bit operand (zero flag)
|
|
test_zero_clear
|
|
|
|
test_ovf_set
|
|
andc #0xfd, ccr ; Immediate 8-bit operand (overflow flag)
|
|
test_ovf_clear
|
|
|
|
test_carry_set
|
|
andc #0xfe, ccr ; Immediate 8-bit operand (carry flag)
|
|
test_carry_clear
|
|
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 1
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
|
|
andc_imm8_exr:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
|
|
ldc #0xff, exr
|
|
stc exr, r0l
|
|
test_h_gr8 0x87, r0l
|
|
|
|
;; andc #xx:8,exr
|
|
set_ccr_zero
|
|
andc #0x7f, exr
|
|
test_cc_clear
|
|
stc exr, r0l
|
|
test_h_gr8 0x7, r0l
|
|
|
|
andc #0x3, exr
|
|
stc exr, r0l
|
|
test_h_gr8 0x3, r0l
|
|
|
|
andc #0x1, exr
|
|
stc exr, r0l
|
|
test_h_gr8 0x1, r0l
|
|
|
|
andc #0x0, exr
|
|
stc exr, r0l
|
|
test_h_gr8 0x0, r0l
|
|
|
|
test_h_gr32 0xa5a5a500 er0
|
|
test_gr_a5a5 1
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
.endif ; not h8300 or h8300h
|
|
|
|
pass
|
|
|
|
exit 0
|