Jaydeep Patil 3224e32fb8 sim: riscv: Add support for compressed integer instructions ... Added support for simulation of compressed integer instruction set ("c"). Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions. The compressed instructions are available for models implementing C extension. Such as RV32IC, RV64IC, RV32GC, RV64GC etc. Approved-By: Andrew Burgess <aburgess@redhat.com>		2024-02-13 11:04:04 +00:00
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aarch64
arm
avr
bfin
bpf	sim: bpf: remove support for ldinddw and ldabsdw instructions	2024-01-29 22:25:19 +01:00
common	sim: Fix compile errors	2024-01-12 21:48:25 +02:00
config
cr16
cris	Update copyright year range in header of all files managed by GDB	2024-01-12 15:49:57 +00:00
d10v
example-synacor
frv
ft32
h8300
iq2000
lib	sim prune_warnings	2023-08-19 12:41:32 +09:30
lm32
m32c	Update copyright year range in header of all files managed by GDB	2024-01-12 15:49:57 +00:00
m32r
m68hc11
mcore	Yet another fix for mcore-sim (rotli)	2023-12-18 22:04:25 -07:00
microblaze
mips	Update copyright year range in header of all files managed by GDB	2024-01-12 15:49:57 +00:00
mn10300
moxie
msp430
or1k	Update copyright year range in header of all files managed by GDB	2024-01-12 15:49:57 +00:00
pru	Update copyright year range in header of all files managed by GDB	2024-01-12 15:49:57 +00:00
riscv	sim: riscv: Add support for compressed integer instructions	2024-02-13 11:04:04 +00:00
sh
v850
.gitignore
ChangeLog-2021
local.mk	Update copyright year range in header of all files managed by GDB	2024-01-12 15:49:57 +00:00