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3ad6c19423
The div and mod eBPF instructions are unsigned, but the semantic specification for the simulator incorrectly used signed operators. Correct them to unsigned versions, and correct the ALU tests in the simulator (which incorrectly assumed signed semantics). Tested in bpf-unknown-none. cpu/ChangeLog: 2020-09-08 David Faust <david.faust@oracle.com> * bpf.cpu (define-alu-instructions): Correct semantic operators for div, mod to unsigned versions. sim/ChangeLog: 2020-09-08 David Faust <david.faust@oracle.com> * bpf/sem-be.c: Regenerate. * bpf/sem-le.c: Likewise. sim/testsuite/ChangeLog: 2020-09-08 David Faust <david.faust@oracle.com> * sim/bpf/alu.s: Correct div and mod tests. * sim/bpf/alu32.s: Likewise. |
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| .. | ||
| bpf.cpu | ||
| bpf.opc | ||
| ChangeLog | ||
| cris.cpu | ||
| epiphany.cpu | ||
| epiphany.opc | ||
| fr30.cpu | ||
| fr30.opc | ||
| frv.cpu | ||
| frv.opc | ||
| ip2k.cpu | ||
| ip2k.opc | ||
| iq10.cpu | ||
| iq2000.cpu | ||
| iq2000.opc | ||
| iq2000m.cpu | ||
| lm32.cpu | ||
| lm32.opc | ||
| m32c.cpu | ||
| m32c.opc | ||
| m32r.cpu | ||
| m32r.opc | ||
| mep-avc2.cpu | ||
| mep-avc.cpu | ||
| mep-c5.cpu | ||
| mep-core.cpu | ||
| mep-default.cpu | ||
| mep-ext-cop.cpu | ||
| mep-fmax.cpu | ||
| mep-h1.cpu | ||
| mep-ivc2.cpu | ||
| mep-rhcop.cpu | ||
| mep-sample-ucidsp.cpu | ||
| mep.cpu | ||
| mep.opc | ||
| mt.cpu | ||
| mt.opc | ||
| or1k.cpu | ||
| or1k.opc | ||
| or1kcommon.cpu | ||
| or1korbis.cpu | ||
| or1korfpx.cpu | ||
| sh64-compact.cpu | ||
| sh64-media.cpu | ||
| sh.cpu | ||
| sh.opc | ||
| simplify.inc | ||
| xc16x.cpu | ||
| xc16x.opc | ||
| xstormy16.cpu | ||
| xstormy16.opc | ||