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A simulator port for the TI PRU I/O processor. v1: https://sourceware.org/ml/gdb-patches/2016-12/msg00143.html v2: https://sourceware.org/ml/gdb-patches/2017-02/msg00397.html v3: https://sourceware.org/ml/gdb-patches/2017-02/msg00516.html v4: https://sourceware.org/ml/gdb-patches/2018-06/msg00484.html v5: https://sourceware.org/ml/gdb-patches/2019-08/msg00584.html v6: https://sourceware.org/ml/gdb-patches/2019-09/msg00036.html gdb/ChangeLog: * NEWS: Mention new simulator port for PRU. sim/ChangeLog: * MAINTAINERS: Add myself as PRU maintainer. * configure: Regenerated. * configure.tgt: Add PRU. sim/common/ChangeLog: * gennltvals.sh: Add PRU libgloss target. * nltvals.def: Regenerate from the latest libgloss sources. sim/pru/ChangeLog: * Makefile.in: New file. * aclocal.m4: Regenerated. * config.in: Regenerated. * configure: Regenerated. * configure.ac: New file. * interp.c: New file. * pru.h: New file. * pru.isa: New file. * sim-main.h: New file.
92 lines
3.3 KiB
C
92 lines
3.3 KiB
C
/* Copyright 2016-2019 Free Software Foundation, Inc.
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Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
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This file is part of the PRU simulator.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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#ifndef PRU_SIM_MAIN
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#define PRU_SIM_MAIN
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#include <stdint.h>
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#include <stddef.h>
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#include "pru.h"
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#include "sim-basics.h"
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#include "sim-base.h"
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/* The machine state.
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This state is maintained in host byte order. The
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fetch/store register functions must translate between host
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byte order and the target processor byte order.
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Keeping this data in target byte order simplifies the register
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read/write functions. Keeping this data in host order improves
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the performance of the simulator. Simulation speed is deemed more
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important. */
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/* For clarity, please keep the same relative order in this enum as in the
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corresponding group of GP registers.
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In PRU ISA, Multiplier-Accumulator-Unit's registers are like "shadows" of
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the GP registers. MAC registers are implicitly addressed when executing
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the XIN/XOUT instructions to access them. Transfer to/from a MAC register
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can happen only from/to its corresponding GP peer register. */
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enum pru_macreg_id {
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/* MAC register CPU GP register Description. */
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PRU_MACREG_MODE, /* r25 */ /* Mode (MUL/MAC). */
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PRU_MACREG_PROD_L, /* r26 */ /* Lower 32 bits of product. */
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PRU_MACREG_PROD_H, /* r27 */ /* Higher 32 bits of product. */
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PRU_MACREG_OP_0, /* r28 */ /* First operand. */
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PRU_MACREG_OP_1, /* r29 */ /* Second operand. */
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PRU_MACREG_ACC_L, /* N/A */ /* Accumulator (not exposed) */
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PRU_MACREG_ACC_H, /* N/A */ /* Higher 32 bits of MAC
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accumulator. */
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PRU_MAC_NREGS
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};
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struct pru_regset
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{
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uint32_t regs[32]; /* Primary registers. */
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uint16_t pc; /* IMEM _word_ address. */
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uint32_t pc_addr_space_marker; /* IMEM virtual linker offset. This
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is the artificial offset that
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we invent in order to "separate"
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the DMEM and IMEM memory spaces. */
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unsigned int carry : 1;
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uint32_t ctable[32]; /* Constant offsets table for xBCO. */
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uint32_t macregs[PRU_MAC_NREGS];
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uint32_t scratchpads[XFRID_MAX + 1][32];
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struct {
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uint16_t looptop; /* LOOP top (PC of loop instr). */
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uint16_t loopend; /* LOOP end (PC of loop end label). */
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int loop_in_progress; /* Whether to check for PC==loopend. */
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uint32_t loop_counter; /* LOOP counter. */
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} loop;
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int cycles;
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int insts;
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};
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struct _sim_cpu {
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struct pru_regset pru_cpu;
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sim_cpu_base base;
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};
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struct sim_state {
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sim_cpu *cpu[MAX_NR_PROCESSORS];
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sim_state_base base;
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};
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#endif /* PRU_SIM_MAIN */
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