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2fe9c2a0c9
This adds an option for the Qualcomm falkor core, the corresponding gcc patch is here: https://gcc.gnu.org/ml/gcc-patches/2016-11/msg00262.html This was tested with aarch64 and armhf builds and make check and also by building and running SPEC2006. * config/tc-aarch64.c (aarch64_cpus): Add falkor. * config/tc-arm.c (arm_cpus): Likewise. * doc/c-aarch64.texi: Likewise. * doc/c-arm.texi: Likewise.
447 lines
14 KiB
Plaintext
447 lines
14 KiB
Plaintext
@c Copyright (C) 2009-2016 Free Software Foundation, Inc.
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@c Contributed by ARM Ltd.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@c man end
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@ifset GENERIC
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@page
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@node AArch64-Dependent
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@chapter AArch64 Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter AArch64 Dependent Features
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@end ifclear
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@cindex AArch64 support
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@menu
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* AArch64 Options:: Options
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* AArch64 Extensions:: Extensions
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* AArch64 Syntax:: Syntax
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* AArch64 Floating Point:: Floating Point
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* AArch64 Directives:: AArch64 Machine Directives
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* AArch64 Opcodes:: Opcodes
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* AArch64 Mapping Symbols:: Mapping Symbols
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@end menu
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@node AArch64 Options
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@section Options
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@cindex AArch64 options (none)
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@cindex options for AArch64 (none)
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@c man begin OPTIONS
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@table @gcctabopt
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@cindex @option{-EB} command line option, AArch64
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@item -EB
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a big-endian processor.
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@cindex @option{-EL} command line option, AArch64
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@item -EL
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a little-endian processor.
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@cindex @option{-mabi=} command line option, AArch64
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@item -mabi=@var{abi}
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Specify which ABI the source code uses. The recognized arguments
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are: @code{ilp32} and @code{lp64}, which decides the generated object
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file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
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@cindex @option{-mcpu=} command line option, AArch64
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@item -mcpu=@var{processor}[+@var{extension}@dots{}]
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This option specifies the target processor. The assembler will issue an error
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message if an attempt is made to assemble an instruction which will not execute
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on the target processor. The following processor names are recognized:
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@code{cortex-a35},
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@code{cortex-a53},
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@code{cortex-a57},
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@code{cortex-a72},
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@code{cortex-a73},
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@code{exynos-m1},
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@code{falkor},
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@code{qdf24xx},
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@code{thunderx},
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@code{vulcan},
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@code{xgene1}
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and
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@code{xgene2}.
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The special name @code{all} may be used to allow the assembler to accept
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instructions valid for any supported processor, including all optional
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extensions.
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In addition to the basic instruction set, the assembler can be told to
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accept, or restrict, various extension mnemonics that extend the
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processor. @xref{AArch64 Extensions}.
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If some implementations of a particular processor can have an
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extension, then then those extensions are automatically enabled.
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Consequently, you will not normally have to specify any additional
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extensions.
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@cindex @option{-march=} command line option, AArch64
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@item -march=@var{architecture}[+@var{extension}@dots{}]
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This option specifies the target architecture. The assembler will
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issue an error message if an attempt is made to assemble an
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instruction which will not execute on the target architecture. The
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following architecture names are recognized: @code{armv8-a},
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@code{armv8.1-a} and @code{armv8.2-a}.
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If both @option{-mcpu} and @option{-march} are specified, the
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assembler will use the setting for @option{-mcpu}. If neither are
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specified, the assembler will default to @option{-mcpu=all}.
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The architecture option can be extended with the same instruction set
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extension options as the @option{-mcpu} option. Unlike
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@option{-mcpu}, extensions are not always enabled by default,
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@xref{AArch64 Extensions}.
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@cindex @code{-mverbose-error} command line option, AArch64
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@item -mverbose-error
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This option enables verbose error messages for AArch64 gas. This option
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is enabled by default.
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@cindex @code{-mno-verbose-error} command line option, AArch64
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@item -mno-verbose-error
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This option disables verbose error messages in AArch64 gas.
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@end table
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@c man end
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@node AArch64 Extensions
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@section Architecture Extensions
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The table below lists the permitted architecture extensions that are
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supported by the assembler and the conditions under which they are
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automatically enabled.
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Multiple extensions may be specified, separated by a @code{+}.
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Extension mnemonics may also be removed from those the assembler
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accepts. This is done by prepending @code{no} to the option that adds
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the extension. Extensions that are removed must be listed after all
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extensions that have been added.
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Enabling an extension that requires other extensions will
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automatically cause those extensions to be enabled. Similarly,
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disabling an extension that is required by other extensions will
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automatically cause those extensions to be disabled.
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@multitable @columnfractions .12 .17 .17 .54
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@headitem Extension @tab Minimum Architecture @tab Enabled by default
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@tab Description
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@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
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@tab Enable CRC instructions.
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@item @code{crypto} @tab ARMv8-A @tab No
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@tab Enable cryptographic extensions. This implies @code{fp} and @code{simd}.
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@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
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@tab Enable floating-point extensions.
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@item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
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@tab Enable ARMv8.2 16-bit floating-point support. This implies
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@code{fp}.
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@item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
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@tab Enable Limited Ordering Regions extensions.
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@item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
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@tab Enable Large System extensions.
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@item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
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@tab Enable Privileged Access Never support.
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@item @code{profile} @tab ARMv8.2-A @tab No
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@tab Enable statistical profiling extensions.
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@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
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@tab Enable the Reliability, Availability and Serviceability
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extension.
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@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
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@tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
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@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
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@tab Enable Advanced SIMD extensions. This implies @code{fp}.
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@item @code{sve} @tab ARMv8-A @tab ARMv8-A or later
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@tab Enable the Scalable Vector Extensions.
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@end multitable
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@node AArch64 Syntax
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@section Syntax
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@menu
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* AArch64-Chars:: Special Characters
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* AArch64-Regs:: Register Names
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* AArch64-Relocations:: Relocations
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@end menu
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@node AArch64-Chars
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@subsection Special Characters
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@cindex line comment character, AArch64
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@cindex AArch64 line comment character
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The presence of a @samp{//} on a line indicates the start of a comment
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that extends to the end of the current line. If a @samp{#} appears as
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the first character of a line, the whole line is treated as a comment.
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@cindex line separator, AArch64
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@cindex statement separator, AArch64
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@cindex AArch64 line separator
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The @samp{;} character can be used instead of a newline to separate
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statements.
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@cindex immediate character, AArch64
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@cindex AArch64 immediate character
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The @samp{#} can be optionally used to indicate immediate operands.
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@node AArch64-Regs
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@subsection Register Names
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@cindex AArch64 register names
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@cindex register names, AArch64
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Please refer to the section @samp{4.4 Register Names} of
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@samp{ARMv8 Instruction Set Overview}, which is available at
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@uref{http://infocenter.arm.com}.
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@node AArch64-Relocations
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@subsection Relocations
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@cindex relocations, AArch64
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@cindex AArch64 relocations
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@cindex MOVN, MOVZ and MOVK group relocations, AArch64
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Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
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by prefixing the label with @samp{#:abs_g2:} etc.
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For example to load the 48-bit absolute address of @var{foo} into x0:
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@smallexample
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movz x0, #:abs_g2:foo // bits 32-47, overflow check
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movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
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movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
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@end smallexample
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@cindex ADRP, ADD, LDR/STR group relocations, AArch64
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Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
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instructions can be generated by prefixing the label with
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@samp{:pg_hi21:} and @samp{#:lo12:} respectively.
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For example to use 33-bit (+/-4GB) pc-relative addressing to
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load the address of @var{foo} into x0:
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@smallexample
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adrp x0, :pg_hi21:foo
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add x0, x0, #:lo12:foo
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@end smallexample
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Or to load the value of @var{foo} into x0:
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@smallexample
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adrp x0, :pg_hi21:foo
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ldr x0, [x0, #:lo12:foo]
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@end smallexample
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Note that @samp{:pg_hi21:} is optional.
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@smallexample
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adrp x0, foo
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@end smallexample
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is equivalent to
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@smallexample
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adrp x0, :pg_hi21:foo
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@end smallexample
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@node AArch64 Floating Point
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@section Floating Point
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@cindex floating point, AArch64 (@sc{ieee})
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@cindex AArch64 floating point (@sc{ieee})
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The AArch64 architecture uses @sc{ieee} floating-point numbers.
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@node AArch64 Directives
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@section AArch64 Machine Directives
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@cindex machine directives, AArch64
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@cindex AArch64 machine directives
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@table @code
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@c AAAAAAAAAAAAAAAAAAAAAAAAA
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@cindex @code{.arch} directive, AArch64
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@item .arch @var{name}
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Select the target architecture. Valid values for @var{name} are the same as
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for the @option{-march} commandline option.
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Specifying @code{.arch} clears any previously selected architecture
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extensions.
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@cindex @code{.arch_extension} directive, AArch64
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@item .arch_extension @var{name}
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Add or remove an architecture extension to the target architecture. Valid
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values for @var{name} are the same as those accepted as architectural
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extensions by the @option{-mcpu} commandline option.
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@code{.arch_extension} may be used multiple times to add or remove extensions
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incrementally to the architecture being compiled for.
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@c BBBBBBBBBBBBBBBBBBBBBBBBBB
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@cindex @code{.bss} directive, AArch64
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@item .bss
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This directive switches to the @code{.bss} section.
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@c CCCCCCCCCCCCCCCCCCCCCCCCCC
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@cindex @code{.cpu} directive, AArch64
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@item .cpu @var{name}
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Set the target processor. Valid values for @var{name} are the same as
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those accepted by the @option{-mcpu=} command line option.
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@c DDDDDDDDDDDDDDDDDDDDDDDDDD
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@cindex @code{.dword} directive, AArch64
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@item .dword @var{expressions}
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The @code{.dword} directive produces 64 bit values.
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@c EEEEEEEEEEEEEEEEEEEEEEEEEE
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@cindex @code{.even} directive, AArch64
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@item .even
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The @code{.even} directive aligns the output on the next even byte
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boundary.
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@c FFFFFFFFFFFFFFFFFFFFFFFFFF
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@c GGGGGGGGGGGGGGGGGGGGGGGGGG
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@c HHHHHHHHHHHHHHHHHHHHHHHHHH
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@c IIIIIIIIIIIIIIIIIIIIIIIIII
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@cindex @code{.inst} directive, AArch64
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@item .inst @var{expressions}
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Inserts the expressions into the output as if they were instructions,
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rather than data.
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@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
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@c KKKKKKKKKKKKKKKKKKKKKKKKKK
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@c LLLLLLLLLLLLLLLLLLLLLLLLLL
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@cindex @code{.ltorg} directive, AArch64
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@item .ltorg
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This directive causes the current contents of the literal pool to be
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dumped into the current section (which is assumed to be the .text
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section) at the current location (aligned to a word boundary).
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GAS maintains a separate literal pool for each section and each
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sub-section. The @code{.ltorg} directive will only affect the literal
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pool of the current section and sub-section. At the end of assembly
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all remaining, un-empty literal pools will automatically be dumped.
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Note - older versions of GAS would dump the current literal
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pool any time a section change occurred. This is no longer done, since
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it prevents accurate control of the placement of literal pools.
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@c MMMMMMMMMMMMMMMMMMMMMMMMMM
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@c NNNNNNNNNNNNNNNNNNNNNNNNNN
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@c OOOOOOOOOOOOOOOOOOOOOOOOOO
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@c PPPPPPPPPPPPPPPPPPPPPPPPPP
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@cindex @code{.pool} directive, AArch64
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@item .pool
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This is a synonym for .ltorg.
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@c QQQQQQQQQQQQQQQQQQQQQQQQQQ
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@c RRRRRRRRRRRRRRRRRRRRRRRRRR
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@cindex @code{.req} directive, AArch64
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@item @var{name} .req @var{register name}
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This creates an alias for @var{register name} called @var{name}. For
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example:
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@smallexample
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foo .req w0
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@end smallexample
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@c SSSSSSSSSSSSSSSSSSSSSSSSSS
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@c TTTTTTTTTTTTTTTTTTTTTTTTTT
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@cindex @code{.tlsdescadd} directive, AArch64
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@item @code{.tlsdescadd}
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Emits a TLSDESC_ADD reloc on the next instruction.
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@cindex @code{.tlsdesccall} directive, AArch64
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@item @code{.tlsdesccall}
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Emits a TLSDESC_CALL reloc on the next instruction.
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@cindex @code{.tlsdescldr} directive, AArch64
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@item @code{.tlsdescldr}
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Emits a TLSDESC_LDR reloc on the next instruction.
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@c UUUUUUUUUUUUUUUUUUUUUUUUUU
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@cindex @code{.unreq} directive, AArch64
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@item .unreq @var{alias-name}
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This undefines a register alias which was previously defined using the
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@code{req} directive. For example:
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@smallexample
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foo .req w0
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.unreq foo
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@end smallexample
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An error occurs if the name is undefined. Note - this pseudo op can
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be used to delete builtin in register name aliases (eg 'w0'). This
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should only be done if it is really necessary.
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@c VVVVVVVVVVVVVVVVVVVVVVVVVV
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@c WWWWWWWWWWWWWWWWWWWWWWWWWW
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@c XXXXXXXXXXXXXXXXXXXXXXXXXX
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@cindex @code{.xword} directive, AArch64
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@item .xword @var{expressions}
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The @code{.xword} directive produces 64 bit values. This is the same
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as the @code{.dword} directive.
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@c YYYYYYYYYYYYYYYYYYYYYYYYYY
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@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
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@end table
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@node AArch64 Opcodes
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@section Opcodes
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@cindex AArch64 opcodes
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@cindex opcodes for AArch64
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GAS implements all the standard AArch64 opcodes. It also
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implements several pseudo opcodes, including several synthetic load
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instructions.
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@table @code
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@cindex @code{LDR reg,=<expr>} pseudo op, AArch64
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@item LDR =
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@smallexample
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ldr <register> , =<expression>
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@end smallexample
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The constant expression will be placed into the nearest literal pool (if it not
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already there) and a PC-relative LDR instruction will be generated.
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@end table
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For more information on the AArch64 instruction set and assembly language
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notation, see @samp{ARMv8 Instruction Set Overview} available at
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@uref{http://infocenter.arm.com}.
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@node AArch64 Mapping Symbols
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@section Mapping Symbols
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The AArch64 ELF specification requires that special symbols be inserted
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into object files to mark certain features:
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@table @code
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@cindex @code{$x}
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@item $x
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At the start of a region of code containing AArch64 instructions.
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@cindex @code{$d}
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@item $d
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At the start of a region of data.
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@end table
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