mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-15 04:31:49 +08:00
391 lines
8.5 KiB
C
391 lines
8.5 KiB
C
#include <stdio.h>
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#include <ctype.h>
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#include "ansidecl.h"
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#include "gdb/callback.h"
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#include "opcode/mn10300.h"
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#include <limits.h>
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#include "gdb/remote-sim.h"
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#include "bfd.h"
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#ifndef INLINE
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#ifdef __GNUC__
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#define INLINE inline
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#else
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#define INLINE
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#endif
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#endif
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extern host_callback *mn10300_callback;
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extern SIM_DESC simulator;
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#define DEBUG_TRACE 0x00000001
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#define DEBUG_VALUES 0x00000002
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extern int mn10300_debug;
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#if UCHAR_MAX == 255
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typedef unsigned char uint8;
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typedef signed char int8;
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#else
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#error "Char is not an 8-bit type"
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#endif
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#if SHRT_MAX == 32767
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typedef unsigned short uint16;
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typedef signed short int16;
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#else
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#error "Short is not a 16-bit type"
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#endif
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#if INT_MAX == 2147483647
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typedef unsigned int uint32;
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typedef signed int int32;
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#else
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# if LONG_MAX == 2147483647
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typedef unsigned long uint32;
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typedef signed long int32;
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# else
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# error "Neither int nor long is a 32-bit type"
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# endif
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#endif
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typedef uint32 reg_t;
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struct simops
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{
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long opcode;
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long mask;
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void (*func)();
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int length;
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int format;
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int numops;
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int operands[16];
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};
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/* The current state of the processor; registers, memory, etc. */
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struct _state
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{
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reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
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lir, lar, mdrq, plus some room for processor
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specific regs. */
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uint8 *mem; /* main memory */
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int exception;
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int exited;
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/* All internal state modified by signal_exception() that may need to be
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rolled back for passing moment-of-exception image back to gdb. */
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reg_t exc_trigger_regs[32];
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reg_t exc_suspend_regs[32];
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int exc_suspended;
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#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
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#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
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#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
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};
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extern struct _state State;
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extern uint32 OP[4];
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extern struct simops Simops[];
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#define PC (State.regs[REG_PC])
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#define SP (State.regs[REG_SP])
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#define PSW (State.regs[11])
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#define PSW_Z 0x1
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#define PSW_N 0x2
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#define PSW_C 0x4
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#define PSW_V 0x8
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#define PSW_IE LSBIT (11)
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#define PSW_LM LSMASK (10, 8)
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#define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
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#define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
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#define REG_D0 0
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#define REG_A0 4
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#define REG_SP 8
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#define REG_PC 9
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#define REG_MDR 10
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#define REG_PSW 11
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#define REG_LIR 12
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#define REG_LAR 13
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#define REG_MDRQ 14
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#define REG_E0 15
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#define REG_SSP 23
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#define REG_MSP 24
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#define REG_USP 25
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#define REG_MCRH 26
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#define REG_MCRL 27
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#define REG_MCVF 28
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#if WITH_COMMON
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/* These definitions conflict with similar macros in common. */
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#else
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#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
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/* sign-extend a 4-bit number */
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#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
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/* sign-extend a 5-bit number */
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#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
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/* sign-extend an 8-bit number */
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#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
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/* sign-extend a 9-bit number */
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#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
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/* sign-extend a 16-bit number */
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#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
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/* sign-extend a 22-bit number */
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#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
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#define MAX32 0x7fffffffLL
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#define MIN32 0xff80000000LL
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#define MASK32 0xffffffffLL
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#define MASK40 0xffffffffffLL
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#endif /* not WITH_COMMON */
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#ifdef _WIN32
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#define SIGTRAP 5
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#define SIGQUIT 3
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#endif
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#if WITH_COMMON
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#define FETCH32(a,b,c,d) \
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((a)+((b)<<8)+((c)<<16)+((d)<<24))
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#define FETCH24(a,b,c) \
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((a)+((b)<<8)+((c)<<16))
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#define FETCH16(a,b) ((a)+((b)<<8))
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#define load_byte(ADDR) \
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sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
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#define load_half(ADDR) \
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sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
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#define load_word(ADDR) \
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sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
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#define store_byte(ADDR, DATA) \
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sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
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PC, write_map, (ADDR), (DATA))
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#define store_half(ADDR, DATA) \
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sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
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PC, write_map, (ADDR), (DATA))
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#define store_word(ADDR, DATA) \
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sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
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PC, write_map, (ADDR), (DATA))
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#endif /* WITH_COMMON */
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#if WITH_COMMON
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#else
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#define load_mem_big(addr,len) \
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(len == 1 ? *((addr) + State.mem) : \
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len == 2 ? ((*((addr) + State.mem) << 8) \
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| *(((addr) + 1) + State.mem)) : \
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len == 3 ? ((*((addr) + State.mem) << 16) \
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| (*(((addr) + 1) + State.mem) << 8) \
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| *(((addr) + 2) + State.mem)) : \
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((*((addr) + State.mem) << 24) \
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| (*(((addr) + 1) + State.mem) << 16) \
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| (*(((addr) + 2) + State.mem) << 8) \
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| *(((addr) + 3) + State.mem)))
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static INLINE uint32
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load_byte (addr)
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SIM_ADDR addr;
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{
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uint8 *p = (addr & 0xffffff) + State.mem;
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#ifdef CHECK_ADDR
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if ((addr & 0xffffff) > max_mem)
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abort ();
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#endif
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return p[0];
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}
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static INLINE uint32
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load_half (addr)
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SIM_ADDR addr;
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{
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uint8 *p = (addr & 0xffffff) + State.mem;
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#ifdef CHECK_ADDR
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if ((addr & 0xffffff) > max_mem)
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abort ();
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#endif
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return p[1] << 8 | p[0];
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}
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static INLINE uint32
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load_3_byte (addr)
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SIM_ADDR addr;
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{
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uint8 *p = (addr & 0xffffff) + State.mem;
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#ifdef CHECK_ADDR
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if ((addr & 0xffffff) > max_mem)
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abort ();
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#endif
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return p[2] << 16 | p[1] << 8 | p[0];
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}
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static INLINE uint32
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load_word (addr)
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SIM_ADDR addr;
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{
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uint8 *p = (addr & 0xffffff) + State.mem;
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#ifdef CHECK_ADDR
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if ((addr & 0xffffff) > max_mem)
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abort ();
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#endif
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return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
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}
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static INLINE uint32
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load_mem (addr, len)
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SIM_ADDR addr;
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int len;
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{
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uint8 *p = (addr & 0xffffff) + State.mem;
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#ifdef CHECK_ADDR
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if ((addr & 0xffffff) > max_mem)
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abort ();
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#endif
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switch (len)
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{
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case 1:
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return p[0];
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case 2:
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return p[1] << 8 | p[0];
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case 3:
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return p[2] << 16 | p[1] << 8 | p[0];
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case 4:
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return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
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default:
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abort ();
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}
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}
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static INLINE void
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store_byte (addr, data)
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SIM_ADDR addr;
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uint32 data;
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{
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uint8 *p = (addr & 0xffffff) + State.mem;
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#ifdef CHECK_ADDR
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if ((addr & 0xffffff) > max_mem)
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abort ();
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#endif
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p[0] = data;
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}
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static INLINE void
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store_half (addr, data)
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SIM_ADDR addr;
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uint32 data;
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{
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uint8 *p = (addr & 0xffffff) + State.mem;
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#ifdef CHECK_ADDR
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if ((addr & 0xffffff) > max_mem)
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abort ();
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#endif
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p[0] = data;
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p[1] = data >> 8;
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}
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static INLINE void
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store_3_byte (addr, data)
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SIM_ADDR addr;
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uint32 data;
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{
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uint8 *p = (addr & 0xffffff) + State.mem;
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#ifdef CHECK_ADDR
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if ((addr & 0xffffff) > max_mem)
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abort ();
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#endif
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p[0] = data;
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p[1] = data >> 8;
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p[2] = data >> 16;
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}
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static INLINE void
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store_word (addr, data)
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SIM_ADDR addr;
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uint32 data;
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{
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uint8 *p = (addr & 0xffffff) + State.mem;
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#ifdef CHECK_ADDR
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if ((addr & 0xffffff) > max_mem)
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abort ();
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#endif
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p[0] = data;
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p[1] = data >> 8;
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p[2] = data >> 16;
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p[3] = data >> 24;
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}
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#endif /* not WITH_COMMON */
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/* Function declarations. */
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uint32 get_word PARAMS ((uint8 *));
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uint16 get_half PARAMS ((uint8 *));
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uint8 get_byte PARAMS ((uint8 *));
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void put_word PARAMS ((uint8 *, uint32));
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void put_half PARAMS ((uint8 *, uint16));
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void put_byte PARAMS ((uint8 *, uint8));
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extern uint8 *map PARAMS ((SIM_ADDR addr));
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INLINE_SIM_MAIN (void) genericAdd PARAMS ((unsigned32 source, unsigned32 destReg));
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INLINE_SIM_MAIN (void) genericSub PARAMS ((unsigned32 source, unsigned32 destReg));
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INLINE_SIM_MAIN (void) genericCmp PARAMS ((unsigned32 leftOpnd, unsigned32 rightOpnd));
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INLINE_SIM_MAIN (void) genericOr PARAMS ((unsigned32 source, unsigned32 destReg));
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INLINE_SIM_MAIN (void) genericXor PARAMS ((unsigned32 source, unsigned32 destReg));
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INLINE_SIM_MAIN (void) genericBtst PARAMS ((unsigned32 leftOpnd, unsigned32 rightOpnd));
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INLINE_SIM_MAIN (int) syscall_read_mem PARAMS ((host_callback *cb,
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struct cb_syscall *sc,
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unsigned long taddr,
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char *buf,
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int bytes));
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INLINE_SIM_MAIN (int) syscall_write_mem PARAMS ((host_callback *cb,
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struct cb_syscall *sc,
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unsigned long taddr,
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const char *buf,
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int bytes));
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INLINE_SIM_MAIN (void) do_syscall PARAMS ((void));
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void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);
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void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
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void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
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void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
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