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38bf472a15
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with the MIPS16e2 ASE as per documentation, including in particular: 1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW MIPS16e2 instructions[1], for assembly and disassembly, 2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE regular MIPS instructions[2], for assembly and disassembly, 3. ELF binary file annotation for the interAptiv MR2 MIPS architecture extension. 4. Support for interAptiv MR2 architecture selection for assembly, in the form of the `-march=interaptiv-mr2' command-line option and its corresponding `arch=interaptiv-mr2' setting for the `.set' and `.module' pseudo-ops. 5. Support for interAptiv MR2 architecture selection for disassembly, in the form of the `mips:interaptiv-mr2' target architecture, for use e.g. with the `-m' command-line option for `objdump'. Parts of this change by Matthew Fortune and Andrew Bennett. References: [1] "MIPS32 interAptiv Multiprocessing System Software User's Manual", Imagination Technologies Ltd., Document Number: MD00904, Revision 02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific Instructions", pp. 878-883 [2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917 include/ * elf/mips.h (E_MIPS_MACH_IAMR2): New macro. (AFL_EXT_INTERAPTIV_MR2): Likewise. * opcode/mips.h: Document new operand codes defined. (INSN_INTERAPTIV_MR2): New macro. (INSN_CHIP_MASK): Adjust accordingly. (CPU_INTERAPTIV_MR2): New macro. (cpu_is_member) <CPU_INTERAPTIV_MR2>: New case. (MIPS16_ALL_ARGS): Rename to... (MIPS_SVRS_ALL_ARGS): ... this. (MIPS16_ALL_STATICS): Rename to... (MIPS_SVRS_ALL_STATICS): ... this. bfd/ * archures.c (bfd_mach_mips_interaptiv_mr2): New macro. * cpu-mips.c (I_interaptiv_mr2): New enum value. (arch_info_struct): Add "mips:interaptiv-mr2" entry. * elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New case. (mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise. (bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. (mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and `bfd_mach_mips_interaptiv_mr2' entries. * bfd-in2.h: Regenerate. opcodes/ * mips-formats.h (INT_BIAS): New macro. (INT_ADJ): Redefine in INT_BIAS terms. * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry. (mips_print_save_restore): New function. (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment. (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort' call. (print_insn_args): Handle OP_SAVE_RESTORE_LIST. (print_mips16_insn_arg): Call `mips_print_save_restore' for OP_SAVE_RESTORE_LIST handling, factored out from here. * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case. (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros. (mips_builtin_opcodes): Add "restore" and "save" entries. * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases. (IAMR2): New macro. (mips16_opcodes): Add "copyw" and "ucopyw" entries. binutils/ * readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. * NEWS: Mention Imagination interAptiv MR2 processor support. gas/ * config/tc-mips.c (validate_mips_insn): Handle OP_SAVE_RESTORE_LIST specially. (mips_encode_save_restore, mips16_encode_save_restore): New functions. (match_save_restore_list_operand): Factor out SAVE/RESTORE operand insertion into the instruction word or halfword to these new functions. (mips_cpu_info_table): Add "interaptiv-mr2" entry. * doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the `-march=' argument list.
148 lines
4.2 KiB
C
148 lines
4.2 KiB
C
/* mips-formats.h
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Copyright (C) 2013-2017 Free Software Foundation, Inc.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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/* For ARRAY_SIZE. */
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#include "libiberty.h"
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#define INT_BIAS(SIZE, LSB, MAX_VAL, BIAS, SHIFT, PRINT_HEX) \
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{ \
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static const struct mips_int_operand op = { \
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{ OP_INT, SIZE, LSB }, MAX_VAL, BIAS, SHIFT, PRINT_HEX \
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}; \
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return &op.root; \
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}
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#define INT_ADJ(SIZE, LSB, MAX_VAL, SHIFT, PRINT_HEX) \
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INT_BIAS(SIZE, LSB, MAX_VAL, 0, SHIFT, PRINT_HEX)
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#define UINT(SIZE, LSB) \
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INT_ADJ(SIZE, LSB, (1 << (SIZE)) - 1, 0, FALSE)
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#define SINT(SIZE, LSB) \
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INT_ADJ(SIZE, LSB, (1 << ((SIZE) - 1)) - 1, 0, FALSE)
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#define HINT(SIZE, LSB) \
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INT_ADJ(SIZE, LSB, (1 << (SIZE)) - 1, 0, TRUE)
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#define BIT(SIZE, LSB, BIAS) \
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{ \
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static const struct mips_int_operand op = { \
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{ OP_INT, SIZE, LSB }, (1 << (SIZE)) - 1, BIAS, 0, TRUE \
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}; \
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return &op.root; \
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}
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#define MAPPED_INT(SIZE, LSB, MAP, PRINT_HEX) \
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{ \
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typedef char ATTRIBUTE_UNUSED \
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static_assert[(1 << (SIZE)) == ARRAY_SIZE (MAP)]; \
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static const struct mips_mapped_int_operand op = { \
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{ OP_MAPPED_INT, SIZE, LSB }, MAP, PRINT_HEX \
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}; \
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return &op.root; \
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}
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#define MSB(SIZE, LSB, BIAS, ADD_LSB, OPSIZE) \
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{ \
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static const struct mips_msb_operand op = { \
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{ OP_MSB, SIZE, LSB }, BIAS, ADD_LSB, OPSIZE \
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}; \
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return &op.root; \
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}
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#define REG(SIZE, LSB, BANK) \
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{ \
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static const struct mips_reg_operand op = { \
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{ OP_REG, SIZE, LSB }, OP_REG_##BANK, 0 \
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}; \
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return &op.root; \
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}
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#define OPTIONAL_REG(SIZE, LSB, BANK) \
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{ \
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static const struct mips_reg_operand op = { \
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{ OP_OPTIONAL_REG, SIZE, LSB }, OP_REG_##BANK, 0 \
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}; \
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return &op.root; \
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}
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#define MAPPED_REG(SIZE, LSB, BANK, MAP) \
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{ \
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typedef char ATTRIBUTE_UNUSED \
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static_assert[(1 << (SIZE)) == ARRAY_SIZE (MAP)]; \
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static const struct mips_reg_operand op = { \
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{ OP_REG, SIZE, LSB }, OP_REG_##BANK, MAP \
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}; \
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return &op.root; \
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}
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#define OPTIONAL_MAPPED_REG(SIZE, LSB, BANK, MAP) \
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{ \
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typedef char ATTRIBUTE_UNUSED \
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static_assert[(1 << (SIZE)) == ARRAY_SIZE (MAP)]; \
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static const struct mips_reg_operand op = { \
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{ OP_OPTIONAL_REG, SIZE, LSB }, OP_REG_##BANK, MAP \
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}; \
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return &op.root; \
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}
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#define REG_PAIR(SIZE, LSB, BANK, MAP) \
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{ \
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typedef char ATTRIBUTE_UNUSED \
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static_assert1[(1 << (SIZE)) == ARRAY_SIZE (MAP##1)]; \
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typedef char ATTRIBUTE_UNUSED \
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static_assert2[(1 << (SIZE)) == ARRAY_SIZE (MAP##2)]; \
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static const struct mips_reg_pair_operand op = { \
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{ OP_REG_PAIR, SIZE, LSB }, OP_REG_##BANK, MAP##1, MAP##2 \
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}; \
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return &op.root; \
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}
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#define PCREL(SIZE, LSB, IS_SIGNED, SHIFT, ALIGN_LOG2, INCLUDE_ISA_BIT, \
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FLIP_ISA_BIT) \
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{ \
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static const struct mips_pcrel_operand op = { \
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{ { OP_PCREL, SIZE, LSB }, \
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(1 << ((SIZE) - (IS_SIGNED))) - 1, 0, SHIFT, TRUE }, \
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ALIGN_LOG2, INCLUDE_ISA_BIT, FLIP_ISA_BIT \
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}; \
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return &op.root.root; \
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}
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#define JUMP(SIZE, LSB, SHIFT) \
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PCREL (SIZE, LSB, FALSE, SHIFT, SIZE + SHIFT, TRUE, FALSE)
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#define JALX(SIZE, LSB, SHIFT) \
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PCREL (SIZE, LSB, FALSE, SHIFT, SIZE + SHIFT, TRUE, TRUE)
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#define BRANCH(SIZE, LSB, SHIFT) \
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PCREL (SIZE, LSB, TRUE, SHIFT, 0, TRUE, FALSE)
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#define SPECIAL(SIZE, LSB, TYPE) \
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{ \
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static const struct mips_operand op = { OP_##TYPE, SIZE, LSB }; \
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return &op; \
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}
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#define PREV_CHECK(SIZE, LSB, GT_OK, LT_OK, EQ_OK, ZERO_OK) \
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{ \
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static const struct mips_check_prev_operand op = { \
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{ OP_CHECK_PREV, SIZE, LSB }, GT_OK, LT_OK, EQ_OK, ZERO_OK \
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}; \
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return &op.root; \
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}
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