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182 lines
6.1 KiB
C
182 lines
6.1 KiB
C
/* Collection of junk for CRIS.
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Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009
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Free Software Foundation, Inc.
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Contributed by Axis Communications.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* For other arch:s, this file is described as a "collection of junk", so
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let's collect some nice junk of our own. Keep it; it might be useful
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some day! */
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#ifndef CRIS_SIM_H
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#define CRIS_SIM_H
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typedef struct {
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/* Whether the branch for the current insn was taken. Placed first
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here, in hope it'll get closer to the main simulator data. */
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USI branch_taken;
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/* PC of the insn of the branch. */
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USI old_pc;
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/* Static cycle count for all insns executed so far, including
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non-context-specific stall cycles, for example when adding to PC. */
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unsigned64 basic_cycle_count;
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/* Stall cycles for unaligned access of memory operands. FIXME:
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Should or should not include unaligned [PC+] operands? */
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unsigned64 unaligned_mem_dword_count;
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/* Context-specific stall cycles. */
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unsigned64 memsrc_stall_count;
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unsigned64 memraw_stall_count;
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unsigned64 movemsrc_stall_count;
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unsigned64 movemaddr_stall_count;
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unsigned64 movemdst_stall_count;
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unsigned64 mulsrc_stall_count;
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unsigned64 jumpsrc_stall_count;
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unsigned64 branch_stall_count;
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unsigned64 jumptarget_stall_count;
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/* What kind of target-specific trace to perform. */
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int flags;
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/* Just the basic cycle count. */
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#define FLAG_CRIS_MISC_PROFILE_SIMPLE 1
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/* Show unaligned accesses. */
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#define FLAG_CRIS_MISC_PROFILE_UNALIGNED 2
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/* Show schedulable entities. */
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#define FLAG_CRIS_MISC_PROFILE_SCHEDULABLE 4
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/* Show everything. */
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#define FLAG_CRIS_MISC_PROFILE_ALL \
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(FLAG_CRIS_MISC_PROFILE_SIMPLE \
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| FLAG_CRIS_MISC_PROFILE_UNALIGNED \
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| FLAG_CRIS_MISC_PROFILE_SCHEDULABLE)
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/* Emit trace of each insn, xsim style. */
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#define FLAG_CRIS_MISC_PROFILE_XSIM_TRACE 8
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#define N_CRISV32_BRANCH_PREDICTORS 256
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unsigned char branch_predictors[N_CRISV32_BRANCH_PREDICTORS];
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} CRIS_MISC_PROFILE;
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/* Handler prototypes for functions called from the CGEN description. */
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extern USI cris_bmod_handler (SIM_CPU *, UINT, USI);
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extern void cris_flush_simulator_decode_cache (SIM_CPU *, USI);
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extern USI crisv10f_break_handler (SIM_CPU *, USI, USI);
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extern USI crisv32f_break_handler (SIM_CPU *, USI, USI);
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extern USI cris_break_13_handler (SIM_CPU *, USI, USI, USI, USI, USI, USI,
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USI, USI);
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extern char cris_have_900000xxif;
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enum cris_unknown_syscall_action_type
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{ CRIS_USYSC_MSG_STOP, CRIS_USYSC_MSG_ENOSYS, CRIS_USYSC_QUIET_ENOSYS };
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extern enum cris_unknown_syscall_action_type cris_unknown_syscall_action;
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enum cris_interrupt_type { CRIS_INT_NMI, CRIS_INT_RESET, CRIS_INT_INT };
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extern int crisv10deliver_interrupt (SIM_CPU *,
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enum cris_interrupt_type,
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unsigned int);
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extern int crisv32deliver_interrupt (SIM_CPU *,
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enum cris_interrupt_type,
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unsigned int);
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/* Using GNU syntax (not C99) so we can compile this on RH 6.2
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(egcs-1.1.2/gcc-2.91.66). */
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#define cris_trace_printf(SD, CPU, FMT...) \
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do \
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{ \
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if (TRACE_FILE (STATE_TRACE_DATA (SD)) != NULL) \
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fprintf (TRACE_FILE (CPU_TRACE_DATA (CPU)), FMT); \
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else \
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sim_io_printf (SD, FMT); \
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} \
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while (0)
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#if WITH_PROFILE_MODEL_P
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#define crisv32f_branch_taken(cpu, oldpc, newpc, taken) \
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do \
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{ \
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CPU_CRIS_MISC_PROFILE (cpu)->old_pc = oldpc; \
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CPU_CRIS_MISC_PROFILE (cpu)->branch_taken = taken; \
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} \
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while (0)
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#else
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#define crisv32f_branch_taken(cpu, oldpc, newpc, taken)
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#endif
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#define crisv10f_branch_taken(cpu, oldpc, newpc, taken)
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#define crisv32f_read_supr(cpu, index) \
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(cgen_rtx_error (current_cpu, \
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"Read of support register is unimplemented"), \
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0)
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#define crisv32f_write_supr(cpu, index, val) \
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cgen_rtx_error (current_cpu, \
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"Write to support register is unimplemented") \
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#define crisv32f_rfg_handler(cpu, pc) \
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cgen_rtx_error (current_cpu, "RFG isn't implemented")
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#define crisv32f_halt_handler(cpu, pc) \
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(cgen_rtx_error (current_cpu, "HALT isn't implemented"), 0)
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#define crisv32f_fidxi_handler(cpu, pc, indx) \
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(cgen_rtx_error (current_cpu, "FIDXI isn't implemented"), 0)
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#define crisv32f_ftagi_handler(cpu, pc, indx) \
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(cgen_rtx_error (current_cpu, "FTAGI isn't implemented"), 0)
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#define crisv32f_fidxd_handler(cpu, pc, indx) \
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(cgen_rtx_error (current_cpu, "FIDXD isn't implemented"), 0)
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#define crisv32f_ftagd_handler(cpu, pc, indx) \
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(cgen_rtx_error (current_cpu, "FTAGD isn't implemented"), 0)
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/* We have nothing special to do when interrupts or NMI are enabled
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after having been disabled, so empty macros are enough for these
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hooks. */
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#define crisv32f_interrupts_enabled(cpu)
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#define crisv32f_nmi_enabled(cpu)
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/* Better warn for this case here, because everything needed is
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somewhere within the CPU. Compare to trying to use interrupts and
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NMI, which would fail earlier, when trying to make nonexistent
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external components generate those exceptions. */
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#define crisv32f_single_step_enabled(cpu) \
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((crisv32f_h_qbit_get (cpu) != 0 \
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|| (crisv32f_h_sr_get (cpu, H_SR_SPC) & ~1) != 0) \
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? (cgen_rtx_error (cpu, \
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"single-stepping isn't implemented"), 0) \
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: 0)
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/* We don't need to track the value of the PID register here. */
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#define crisv32f_write_pid_handler(cpu, val)
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/* Neither do we need to know of transitions to user mode. */
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#define crisv32f_usermode_enabled(cpu)
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/* House-keeping exported from traps.c */
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extern void cris_set_callbacks (host_callback *);
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/* FIXME: Add more junk. */
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#endif
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