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1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
253 lines
8.5 KiB
C
253 lines
8.5 KiB
C
/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
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Copyright (C) 2003-2024 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef XTENSA_TDEP_H
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#define XTENSA_TDEP_H
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#include "arch/xtensa.h"
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#include "gdbarch.h"
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#include "xtensa-config.h"
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/* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
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whenever the "tdep" structure changes in an incompatible way. */
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#define XTENSA_TDEP_VERSION 0x60
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/* Xtensa register type. */
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enum xtensa_register_type_t
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{
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xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */
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xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */
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xtRegisterTypeUserReg, /* User defined registers (rur). */
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xtRegisterTypeTieRegfile, /* User define register files. */
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xtRegisterTypeTieState, /* TIE States (mapped on user regs). */
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xtRegisterTypeMapped, /* Mapped on Special Registers. */
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xtRegisterTypeUnmapped, /* Special case of masked registers. */
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xtRegisterTypeWindow, /* Live window registers (a0..a15). */
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xtRegisterTypeVirtual, /* PC, FP. */
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xtRegisterTypeUnknown
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};
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/* Xtensa register group. */
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#define XTENSA_MAX_COPROCESSOR 0x10 /* Number of Xtensa coprocessors. */
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enum xtensa_register_group_t
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{
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xtRegisterGroupUnknown = 0,
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xtRegisterGroupRegFile = 0x0001, /* Register files without ARx. */
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xtRegisterGroupAddrReg = 0x0002, /* ARx. */
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xtRegisterGroupSpecialReg = 0x0004, /* SRxx. */
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xtRegisterGroupUserReg = 0x0008, /* URxx. */
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xtRegisterGroupState = 0x0010, /* States. */
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xtRegisterGroupGeneral = 0x0100, /* General registers, Ax, SR. */
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xtRegisterGroupUser = 0x0200, /* User registers. */
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xtRegisterGroupFloat = 0x0400, /* Floating Point. */
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xtRegisterGroupVectra = 0x0800, /* Vectra. */
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xtRegisterGroupSystem = 0x1000, /* System. */
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xtRegisterGroupNCP = 0x00800000, /* Non-CP non-base opt/custom. */
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xtRegisterGroupCP0 = 0x01000000, /* CP0. */
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xtRegisterGroupCP1 = 0x02000000, /* CP1. */
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xtRegisterGroupCP2 = 0x04000000, /* CP2. */
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xtRegisterGroupCP3 = 0x08000000, /* CP3. */
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xtRegisterGroupCP4 = 0x10000000, /* CP4. */
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xtRegisterGroupCP5 = 0x20000000, /* CP5. */
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xtRegisterGroupCP6 = 0x40000000, /* CP6. */
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xtRegisterGroupCP7 = 0x80000000, /* CP7. */
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};
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/* Xtensa target flags. */
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enum xtensa_target_flags_t
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{
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xtTargetFlagsNonVisibleRegs = 0x0001,
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xtTargetFlagsUseFetchStore = 0x0002,
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};
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/* Mask. */
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typedef struct
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{
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int reg_num;
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int bit_start;
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int bit_size;
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} xtensa_reg_mask_t;
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typedef struct
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{
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int count;
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xtensa_reg_mask_t *mask;
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} xtensa_mask_t;
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/* Xtensa register representation. */
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typedef struct
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{
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const char *name; /* Register name. */
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int offset; /* Offset. */
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xtensa_register_type_t type; /* Register type. */
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xtensa_register_group_t group;/* Register group. */
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struct type* ctype; /* C-type. */
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int bit_size; /* The actual bit size in the target. */
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int byte_size; /* Actual space allocated in registers[]. */
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int align; /* Alignment for this register. */
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unsigned int target_number; /* Register target number. */
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int flags; /* Flags. */
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int coprocessor; /* Coprocessor num, -1 for non-CP, else -2. */
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const xtensa_mask_t *mask; /* Register is a compilation of other regs. */
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const char *fetch; /* Instruction sequence to fetch register. */
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const char *store; /* Instruction sequence to store register. */
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} xtensa_register_t;
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/* For xtensa-config.c to expand to the structure above. */
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#define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
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{#name, ofs, (xtensa_register_type_t) (ty), \
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((xtensa_register_group_t) \
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((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2)))), \
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ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto},
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#define XTREG_END \
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{0, 0, (xtensa_register_type_t) 0, (xtensa_register_group_t) 0, \
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0, 0, 0, 0, (unsigned) -1, 0, 0, 0, 0, 0},
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#define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001
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#define XTENSA_REGISTER_FLAGS_READABLE 0x0002
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#define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004
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#define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008
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/* Call-ABI for stack frame. */
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enum call_abi_t
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{
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CallAbiDefault = 0, /* Any 'callX' instructions; default stack. */
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CallAbiCall0Only, /* Only 'call0' instructions; flat stack. */
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};
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struct ctype_cache
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{
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struct ctype_cache *next;
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int size;
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struct type *virtual_type;
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};
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#ifndef XCHAL_NUM_CONTEXTS
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# define XCHAL_NUM_CONTEXTS 0
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#endif
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#ifndef XCHAL_HAVE_EXCEPTIONS
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# define XCHAL_HAVE_EXCEPTIONS 1
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#endif
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/* Xtensa-specific target dependencies. */
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struct xtensa_gdbarch_tdep : gdbarch_tdep_base
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{
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xtensa_gdbarch_tdep (xtensa_register_t *regmap)
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: regmap (regmap)
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{}
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unsigned int target_flags = 0;
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/* Spill location for TIE register files under ocd. */
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unsigned int spill_location = (unsigned int) -1;
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unsigned int spill_size = 0;
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char *unused = nullptr; /* Placeholder for compatibility. */
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/* Calling convention. */
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call_abi_t call_abi = (XSHAL_ABI == XTHAL_ABI_CALL0
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? CallAbiCall0Only : CallAbiDefault);
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/* CPU configuration. */
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unsigned int debug_interrupt_level = XCHAL_DEBUGLEVEL;
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unsigned int icache_line_bytes = XCHAL_ICACHE_LINESIZE;
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unsigned int dcache_line_bytes = XCHAL_DCACHE_LINESIZE;
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unsigned int dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK;
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unsigned int isa_use_windowed_registers = XSHAL_ABI != XTHAL_ABI_CALL0;
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unsigned int isa_use_density_instructions = XCHAL_HAVE_DENSITY;
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unsigned int isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS;
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unsigned int isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS;
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unsigned int isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE; /* Maximum instruction length. */
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unsigned int debug_num_ibreaks = XCHAL_NUM_IBREAK; /* Number of IBREAKs. */
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unsigned int debug_num_dbreaks = XCHAL_NUM_DBREAK;
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/* Register map. */
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xtensa_register_t *regmap;
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unsigned int num_regs = 0; /* Number of registers in register map. */
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unsigned int num_nopriv_regs = 0; /* Number of non-privileged registers. */
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unsigned int num_pseudo_regs = 0; /* Number of pseudo registers. */
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unsigned int num_aregs = XCHAL_NUM_AREGS; /* Size of register file. */
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unsigned int num_contexts = XCHAL_NUM_CONTEXTS;
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int ar_base = -1; /* Register number for AR0. */
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int a0_base = -1; /* Register number for A0 (pseudo). */
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int wb_regnum = -1; /* Register number for WB. */
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int ws_regnum = -1; /* Register number for WS. */
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int pc_regnum = -1; /* Register number for PC. */
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int ps_regnum = -1; /* Register number for PS. */
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int lbeg_regnum = -1; /* Register numbers for count regs. */
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int lend_regnum = -1;
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int lcount_regnum = -1;
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int sar_regnum = -1; /* Register number of SAR. */
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int litbase_regnum = -1; /* Register number of LITBASE. */
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int threadptr_regnum = -1; /* Register number of THREADPTR. */
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int interrupt_regnum = -1; /* Register number for interrupt. */
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int interrupt2_regnum = -1; /* Register number for interrupt2. */
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int cpenable_regnum = -1; /* Register number for cpenable. */
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int debugcause_regnum = -1; /* Register number for debugcause. */
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int exccause_regnum = -1; /* Register number for exccause. */
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int excvaddr_regnum = -1; /* Register number for excvaddr. */
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int max_register_raw_size = 0;
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int max_register_virtual_size = 0;
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unsigned long *fp_layout = nullptr; /* Layout of custom/TIE regs in 'FP' area. */
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unsigned int fp_layout_bytes = 0; /* Size of layout information (in bytes). */
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unsigned long *gregmap = nullptr;
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/* Cached register types. */
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struct ctype_cache *type_entries = nullptr;
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};
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#define WB_SHIFT 2
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/* We assign fixed numbers to the registers of the "current" window
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(i.e., relative to WB). The registers get remapped via the reg_map
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data structure to their corresponding register in the AR register
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file (see xtensa-tdep.c). */
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#endif /* XTENSA_TDEP_H */
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