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On aarch64-linux, with test-case gdb.base/watch-bitfields.exp I run into:
...
(gdb) continue^M
Continuing.^M
^M
Hardware watchpoint 2: -location q.a^M
^M
Old value = 1^M
New value = 0^M
main () at watch-bitfields.c:42^M
42 q.h--;^M
(gdb) FAIL: $exp: -location watch against bitfields: q.e: 0->5: continue
...
In a minimal form, if we step past line 37 which sets q.e, and we have a
watchpoint set on q.e, it triggers:
...
$ gdb -q -batch watch-bitfields -ex "b 37" -ex run -ex "watch q.e" -ex step
Breakpoint 1 at 0x410204: file watch-bitfields.c, line 37.
Breakpoint 1, main () at watch-bitfields.c:37
37 q.e = 5;
Hardware watchpoint 2: q.e
Hardware watchpoint 2: q.e
Old value = 0
New value = 5
main () at /home/vries/gdb/src/gdb/testsuite/gdb.base/watch-bitfields.c:38
38 q.f = 6;
...
However, if we set in addition a watchpoint on q.a, the watchpoint on q.e
doesn't trigger.
How does this happen?
Bitfield q.a is just bit 0 of byte 0, and bitfield q.e is bit 4..7 of byte 1
and bit 1 of byte 2. So, watch q.a should watch byte 0, and watch q.e should
watch bytes 1 and 2.
Using "maint set show-debug-regs on" (and some more detailed debug prints) we
get:
...
WP2: addr=0x440028 (orig=0x440029), ctrl=0x000000d5, ref.count=1
ctrl: enabled=1, offset=1, len=2
WP3: addr=0x440028 (orig=0x440028), ctrl=0x00000035, ref.count=1
ctrl: enabled=1, offset=0, len=1
...
which matches that.
When executing line 37, a hardware watchpoint trap triggers and we hit
aarch64_stopped_data_address with addr_trap == 0x440028:
...
(gdb) p /x addr_trap
$1 = 0x440028
....
and since the loop in aarch64_stopped_data_address walks backward, we check
WP3 first, which matches, and consequently target_stopped_by_watchpoint
returns true in watchpoints_triggered.
Likewise for target_stopped_data_address, which also returns addr == 0x440028.
Watchpoints_triggered matches watchpoint q.a to that address, and sets
watch_triggered_yes.
However, subsequently the value of q.a is checked, and it's the same value as
before (becase the insn in line 37 didn't change q.a), so the watchpoint
hardware trap is not reported to the user.
The problem originates from that fact that aarch64_stopped_data_address picked
WP3 instead of WP2.
There's something we can do about this. In the example above, both
target_stopped_by_watchpoint and target_stopped_data_address returned true.
Instead we can return true in target_stopped_by_watchpoint but false in
target_stopped_data_address. This lets watchpoints_triggered known that a
watchpoint was triggered, but we don't know where, and both watchpoints
get set to watch_triggered_unknown.
Subsequently, the values of both q.a and q.e are checked, and since q.e is not
the same value as before, the watchpoint hardware trap is reported to the user.
Note that this works well for regular (write) watchpoints (watch command), but
not for read watchpoints (rwatch command), because for those no value is
checked. Likewise for access watchpoints (awatch command).
So, fix this by:
- passing a nullptr in aarch64_fbsd_nat_target::stopped_by_watchpoint and
aarch64_linux_nat_target::stopped_by_watchpoint to make clear we're not
interested in the stop address,
- introducing a two-phase approach in aarch64_stopped_data_address, where:
- phase one handles access and read watchpoints, as before, and
- phase two handles write watchpoints, where multiple matches cause:
- return true if addr_p == null, and
- return false if addr_p != null.
Tested on aarch64-linux.
Approved-By: Luis Machado <luis.machado@arm.com>
PR tdep/31214
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31214
132 lines
5.0 KiB
C
132 lines
5.0 KiB
C
/* Copyright (C) 2009-2024 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef NAT_AARCH64_HW_POINT_H
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#define NAT_AARCH64_HW_POINT_H
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/* Macro definitions, data structures, and code for the hardware
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breakpoint and hardware watchpoint support follow. We use the
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following abbreviations throughout the code:
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hw - hardware
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bp - breakpoint
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wp - watchpoint */
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/* Maximum number of hardware breakpoint and watchpoint registers.
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Neither of these values may exceed the width of dr_changed_t
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measured in bits. */
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#define AARCH64_HBP_MAX_NUM 16
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#define AARCH64_HWP_MAX_NUM 16
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/* Alignment requirement in bytes for addresses written to
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hardware breakpoint and watchpoint value registers.
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A ptrace call attempting to set an address that does not meet the
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alignment criteria will fail. Limited support has been provided in
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this port for unaligned watchpoints, such that from a GDB user
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perspective, an unaligned watchpoint may be requested.
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This is achieved by minimally enlarging the watched area to meet the
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alignment requirement, and if necessary, splitting the watchpoint
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over several hardware watchpoint registers. */
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#define AARCH64_HBP_ALIGNMENT 4
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#define AARCH64_HWP_ALIGNMENT 8
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/* The maximum length of a memory region that can be watched by one
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hardware watchpoint register. */
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#define AARCH64_HWP_MAX_LEN_PER_REG 8
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/* Macro for the expected version of the ARMv8-A debug architecture. */
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#define AARCH64_DEBUG_ARCH_V8 0x6
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#define AARCH64_DEBUG_ARCH_V8_1 0x7
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#define AARCH64_DEBUG_ARCH_V8_2 0x8
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#define AARCH64_DEBUG_ARCH_V8_4 0x9
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#define AARCH64_DEBUG_ARCH_V8_8 0xa
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/* Armv8.9 debug architecture. */
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#define AARCH64_DEBUG_ARCH_V8_9 0xb
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/* ptrace expects control registers to be formatted as follows:
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31 13 5 3 1 0
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+--------------------------------+----------+------+------+----+
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| RESERVED (SBZ) | MASK | TYPE | PRIV | EN |
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+--------------------------------+----------+------+------+----+
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The TYPE field is ignored for breakpoints. */
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#define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
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#define DR_CONTROL_MASK(ctrl) (((ctrl) >> 5) & 0xff)
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#define DR_CONTROL_TYPE(ctrl) (((ctrl) >> 3) & 0x3)
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/* Structure for managing the hardware breakpoint/watchpoint resources.
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DR_ADDR_* stores the address, DR_CTRL_* stores the control register
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content, and DR_REF_COUNT_* counts the numbers of references to the
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corresponding bp/wp, by which way the limited hardware resources
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are not wasted on duplicated bp/wp settings (though so far gdb has
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done a good job by not sending duplicated bp/wp requests). */
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struct aarch64_debug_reg_state
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{
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/* hardware breakpoint */
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CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
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unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
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unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
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/* hardware watchpoint */
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/* Address aligned down to AARCH64_HWP_ALIGNMENT. */
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CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
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/* Address as entered by user without any forced alignment. */
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CORE_ADDR dr_addr_orig_wp[AARCH64_HWP_MAX_NUM];
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unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
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unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
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};
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extern int aarch64_num_bp_regs;
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extern int aarch64_num_wp_regs;
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/* Invoked when IDXth breakpoint/watchpoint register pair needs to be
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updated. */
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void aarch64_notify_debug_reg_change (ptid_t ptid, int is_watchpoint,
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unsigned int idx);
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unsigned int aarch64_watchpoint_offset (unsigned int ctrl);
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unsigned int aarch64_watchpoint_length (unsigned int ctrl);
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enum target_hw_bp_type aarch64_watchpoint_type (unsigned int ctrl);
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int aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
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int len, int is_insert, ptid_t ptid,
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struct aarch64_debug_reg_state *state);
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int aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
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int len, int is_insert, ptid_t ptid,
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struct aarch64_debug_reg_state *state);
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/* Return TRUE if there are any hardware breakpoints. If WATCHPOINT is TRUE,
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check hardware watchpoints instead. */
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bool aarch64_any_set_debug_regs_state (aarch64_debug_reg_state *state,
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bool watchpoint);
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void aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
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const char *func, CORE_ADDR addr,
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int len, enum target_hw_bp_type type);
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int aarch64_region_ok_for_watchpoint (CORE_ADDR addr, int len);
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#endif /* NAT_AARCH64_HW_POINT_H */
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