Richard Sandiford bcca550b3d aarch64: Add BC instruction ... This patch adds support for the Armv8.8-A BC instruction. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions/BC-cond--Branch-Consistent-conditionally-?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_HBC): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_HBC. opcodes/ * aarch64-tbl.h (aarch64_feature_hbc): New variable. (HBC, HBC_INSN): New macros. (aarch64_opcode_table): Add BC.C. * aarch64-dis-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document +hbc. * config/tc-aarch64.c (aarch64_features): Add "hbc". * testsuite/gas/aarch64/hbc.s, testsuite/gas/aarch64/hbc.d: New test. * testsuite/gas/aarch64/hbc-invalid.s, testsuite/gas/aarch64/hbc-invalid.l, testsuite/gas/aarch64/hbc-invalid.d: New test.		2021-12-02 15:00:57 +00:00
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atof-ieee.c
atof-vax.c
bfin-aux.h
bfin-defs.h
bfin-lex-wrapper.c
bfin-lex.l
bfin-parse.y
e-crisaout.c
e-criself.c
e-i386aout.c
e-i386coff.c
e-i386elf.c
e-mipself.c
itbl-mips.h
loongarch-lex-wrapper.c
loongarch-lex.h
loongarch-lex.l
loongarch-parse.y
m68k-parse.h
m68k-parse.y
obj-aout.c
obj-aout.h
obj-coff-seh.c
obj-coff-seh.h
obj-coff.c
obj-coff.h
obj-ecoff.c
obj-ecoff.h
obj-elf.c
obj-elf.h
obj-evax.c
obj-evax.h
obj-fdpicelf.c
obj-fdpicelf.h
obj-macho.c
obj-macho.h
obj-multi.c
obj-multi.h
obj-som.c
obj-som.h
rl78-defs.h
rl78-parse.y
rx-defs.h
rx-parse.y
tc-aarch64.c	aarch64: Add BC instruction	2021-12-02 15:00:57 +00:00
tc-aarch64.h	aarch64: Provide line info for unclosed sequences	2021-12-02 15:00:56 +00:00
tc-alpha.c
tc-alpha.h
tc-arc.c
tc-arc.h
tc-arm.c
tc-arm.h
tc-avr.c
tc-avr.h
tc-bfin.c
tc-bfin.h
tc-bpf.c
tc-bpf.h
tc-cr16.c
tc-cr16.h
tc-cris.c
tc-cris.h
tc-crx.c
tc-crx.h
tc-csky.c
tc-csky.h
tc-d10v.c
tc-d10v.h
tc-d30v.c
tc-d30v.h
tc-dlx.c
tc-dlx.h
tc-epiphany.c
tc-epiphany.h
tc-fr30.c
tc-fr30.h
tc-frv.c
tc-frv.h
tc-ft32.c
tc-ft32.h
tc-generic.c
tc-generic.h
tc-h8300.c
tc-h8300.h
tc-hppa.c
tc-hppa.h
tc-i386-intel.c
tc-i386.c	x86: Don't allow KMOV in TLS code sequences	2021-11-16 07:34:46 -08:00
tc-i386.h
tc-ia64.c
tc-ia64.h
tc-ip2k.c
tc-ip2k.h
tc-iq2000.c
tc-iq2000.h
tc-lm32.c
tc-lm32.h
tc-loongarch.c
tc-loongarch.h
tc-m32c.c
tc-m32c.h
tc-m32r.c
tc-m32r.h
tc-m68hc11.c
tc-m68hc11.h
tc-m68k.c
tc-m68k.h
tc-m68851.h
tc-mcore.c
tc-mcore.h
tc-mep.c
tc-mep.h
tc-metag.c
tc-metag.h
tc-microblaze.c
tc-microblaze.h
tc-mips.c
tc-mips.h
tc-mmix.c
tc-mmix.h
tc-mn10200.c
tc-mn10200.h
tc-mn10300.c
tc-mn10300.h
tc-moxie.c
tc-moxie.h
tc-msp430.c
tc-msp430.h
tc-mt.c
tc-mt.h
tc-nds32.c
tc-nds32.h
tc-nios2.c
tc-nios2.h
tc-ns32k.c
tc-ns32k.h
tc-or1k.c
tc-or1k.h
tc-pdp11.c
tc-pdp11.h
tc-pj.c
tc-pj.h
tc-ppc.c
tc-ppc.h
tc-pru.c
tc-pru.h
tc-riscv.c	RISC-V: Replace .option rvc/norvc with .option arch, +c/-c.	2021-11-22 19:31:29 +08:00
tc-riscv.h	RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.	2021-11-19 09:32:19 +08:00
tc-rl78.c
tc-rl78.h
tc-rx.c
tc-rx.h
tc-s12z.c
tc-s12z.h
tc-s390.c
tc-s390.h
tc-score7.c
tc-score.c
tc-score.h
tc-sh.c
tc-sh.h
tc-sparc.c
tc-sparc.h
tc-spu.c
tc-spu.h
tc-tic4x.c
tc-tic4x.h
tc-tic6x.c
tc-tic6x.h
tc-tic30.c
tc-tic30.h
tc-tic54x.c
tc-tic54x.h
tc-tilegx.c
tc-tilegx.h
tc-tilepro.c
tc-tilepro.h
tc-v850.c
tc-v850.h
tc-vax.c
tc-vax.h
tc-visium.c
tc-visium.h
tc-wasm32.c
tc-wasm32.h
tc-xc16x.c
tc-xc16x.h
tc-xgate.c
tc-xgate.h
tc-xstormy16.c
tc-xstormy16.h
tc-xtensa.c
tc-xtensa.h
tc-z8k.c
tc-z8k.h
tc-z80.c
tc-z80.h
te-386bsd.h
te-aix5.h
te-aix.h
te-armeabi.h
te-armfbsdeabi.h
te-armfbsdvfp.h
te-armlinuxeabi.h
te-cloudabi.h
te-csky_abiv1_linux.h
te-csky_abiv1.h
te-csky_abiv2_linux.h
te-csky_abiv2.h
te-dragonfly.h
te-freebsd.h
te-generic.h
te-gnu.h
te-go32.h
te-haiku.h
te-hppa64.h
te-hppa.h
te-hppalinux64.h
te-hpux.h
te-ia64aix.h
te-interix.h
te-irix.h
te-linux.h
te-lynx.h
te-macos.h
te-nacl.h
te-nbsd532.h
te-nbsd.h
te-pc532mach.h
te-pe.h
te-pep.h
te-solaris.h
te-svr4.h
te-tmips.h
te-uclinux.h
te-vms.c
te-vms.h
te-vxworks.h
te-wince-pe.h
vax-inst.h
xtensa-istack.h
xtensa-relax.c
xtensa-relax.h