mirror of
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The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
567 lines
19 KiB
Plaintext
567 lines
19 KiB
Plaintext
@c Copyright (C) 2009-2022 Free Software Foundation, Inc.
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@c Contributed by ARM Ltd.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@c man end
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@ifset GENERIC
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@page
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@node AArch64-Dependent
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@chapter AArch64 Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter AArch64 Dependent Features
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@end ifclear
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@cindex AArch64 support
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@menu
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* AArch64 Options:: Options
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* AArch64 Extensions:: Extensions
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* AArch64 Syntax:: Syntax
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* AArch64 Floating Point:: Floating Point
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* AArch64 Directives:: AArch64 Machine Directives
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* AArch64 Opcodes:: Opcodes
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* AArch64 Mapping Symbols:: Mapping Symbols
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@end menu
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@node AArch64 Options
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@section Options
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@cindex AArch64 options (none)
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@cindex options for AArch64 (none)
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@c man begin OPTIONS
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@table @gcctabopt
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@cindex @option{-EB} command-line option, AArch64
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@item -EB
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a big-endian processor.
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@cindex @option{-EL} command-line option, AArch64
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@item -EL
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a little-endian processor.
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@cindex @option{-mabi=} command-line option, AArch64
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@item -mabi=@var{abi}
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Specify which ABI the source code uses. The recognized arguments
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are: @code{ilp32} and @code{lp64}, which decides the generated object
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file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
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@cindex @option{-mcpu=} command-line option, AArch64
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@item -mcpu=@var{processor}[+@var{extension}@dots{}]
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This option specifies the target processor. The assembler will issue an error
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message if an attempt is made to assemble an instruction which will not execute
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on the target processor. The following processor names are recognized:
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@code{cortex-a34},
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@code{cortex-a35},
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@code{cortex-a53},
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@code{cortex-a55},
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@code{cortex-a57},
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@code{cortex-a65},
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@code{cortex-a65ae},
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@code{cortex-a72},
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@code{cortex-a73},
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@code{cortex-a75},
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@code{cortex-a76},
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@code{cortex-a76ae},
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@code{cortex-a77},
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@code{cortex-a78},
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@code{cortex-a78ae},
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@code{cortex-a78c},
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@code{cortex-a510},
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@code{cortex-a710},
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@code{ares},
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@code{exynos-m1},
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@code{falkor},
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@code{neoverse-n1},
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@code{neoverse-n2},
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@code{neoverse-e1},
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@code{neoverse-v1},
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@code{qdf24xx},
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@code{saphira},
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@code{thunderx},
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@code{vulcan},
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@code{xgene1}
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@code{xgene2},
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@code{cortex-r82},
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@code{cortex-x1},
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and
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@code{cortex-x2}.
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The special name @code{all} may be used to allow the assembler to accept
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instructions valid for any supported processor, including all optional
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extensions.
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In addition to the basic instruction set, the assembler can be told to
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accept, or restrict, various extension mnemonics that extend the
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processor. @xref{AArch64 Extensions}.
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If some implementations of a particular processor can have an
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extension, then then those extensions are automatically enabled.
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Consequently, you will not normally have to specify any additional
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extensions.
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@cindex @option{-march=} command-line option, AArch64
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@item -march=@var{architecture}[+@var{extension}@dots{}]
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This option specifies the target architecture. The assembler will
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issue an error message if an attempt is made to assemble an
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instruction which will not execute on the target architecture. The
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following architecture names are recognized: @code{armv8-a},
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@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
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@code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8.8-a},
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@code{armv8-r}, @code{armv9-a}, @code{armv9.1-a}, @code{armv9.2-a},
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and @code{armv9.3-a}.
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If both @option{-mcpu} and @option{-march} are specified, the
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assembler will use the setting for @option{-mcpu}. If neither are
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specified, the assembler will default to @option{-mcpu=all}.
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The architecture option can be extended with the same instruction set
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extension options as the @option{-mcpu} option. Unlike
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@option{-mcpu}, extensions are not always enabled by default,
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@xref{AArch64 Extensions}.
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@cindex @code{-mverbose-error} command-line option, AArch64
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@item -mverbose-error
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This option enables verbose error messages for AArch64 gas. This option
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is enabled by default.
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@cindex @code{-mno-verbose-error} command-line option, AArch64
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@item -mno-verbose-error
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This option disables verbose error messages in AArch64 gas.
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@end table
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@c man end
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@node AArch64 Extensions
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@section Architecture Extensions
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The table below lists the permitted architecture extensions that are
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supported by the assembler and the conditions under which they are
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automatically enabled.
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Multiple extensions may be specified, separated by a @code{+}.
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Extension mnemonics may also be removed from those the assembler
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accepts. This is done by prepending @code{no} to the option that adds
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the extension. Extensions that are removed must be listed after all
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extensions that have been added.
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Enabling an extension that requires other extensions will
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automatically cause those extensions to be enabled. Similarly,
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disabling an extension that is required by other extensions will
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automatically cause those extensions to be disabled.
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@multitable @columnfractions .12 .17 .17 .54
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@headitem Extension @tab Minimum Architecture @tab Enabled by default
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@tab Description
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@item @code{aes} @tab ARMv8-A @tab No
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@tab Enable the AES cryptographic extensions. This implies @code{fp} and
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@code{simd}.
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@item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
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@tab Enable BFloat16 extension.
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@item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
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@tab Enable the complex number SIMD extensions. This implies @code{fp16} and
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@code{simd}.
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@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
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@tab Enable CRC instructions.
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@item @code{crypto} @tab ARMv8-A @tab No
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@tab Enable cryptographic extensions. This implies @code{fp}, @code{simd},
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@code{aes} and @code{sha2}.
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@item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
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@tab Enable the Dot Product extension. This implies @code{simd}.
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@item @code{f32mm} @tab ARMv8.2-A @tab No
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@tab Enable F32 Matrix Multiply extension. This implies @code{sve}.
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@item @code{f64mm} @tab ARMv8.2-A @tab No
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@tab Enable F64 Matrix Multiply extension. This implies @code{sve}.
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@item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
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@tab Enable Flag Manipulation instructions.
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@item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
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@tab Enable ARMv8.2 16-bit floating-point multiplication variant support. This
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implies @code{fp} and @code{fp16}.
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@item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
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@tab Enable ARMv8.2 16-bit floating-point support. This implies @code{fp}.
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@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
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@tab Enable floating-point extensions.
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@item @code{hbc} @tab @tab Armv8.8-A or later
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@tab Enable Armv8.8-A hinted conditional branch instructions
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@item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
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@tab Enable Int8 Matrix Multiply extension.
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@item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
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@tab Enable Limited Ordering Regions extensions.
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@item @code{ls64} @tab ARMv8.6-A @tab ARMv8.7-A or later
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@tab Enable 64 Byte Loads/Stores.
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@item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
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@tab Enable Large System extensions.
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@item @code{memtag} @tab ARMv8.5-A @tab No
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@tab Enable ARMv8.5-A Memory Tagging Extensions.
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@item @code{mops} @tab @tab Armv8.8-A or later
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@tab Enable Armv8.8-A memcpy and memset acceleration instructions
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@item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
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@tab Enable Privileged Access Never support.
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@item @code{pauth} @tab ARMv8-A @tab No
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@tab Enable Pointer Authentication.
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@item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
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@tab Enable the Execution and Data and Prediction instructions.
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@item @code{profile} @tab ARMv8.2-A @tab No
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@tab Enable statistical profiling extensions.
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@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
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@tab Enable the Reliability, Availability and Serviceability extension.
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@item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
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@tab Enable the weak release consistency extension.
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@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
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@tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
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@item @code{rng} @tab ARMv8.5-A @tab No
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@tab Enable ARMv8.5-A random number instructions.
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@item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
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@tab Enable the speculation barrier instruction sb.
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@item @code{sha2} @tab ARMv8-A @tab No
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@tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and
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@code{simd}.
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@item @code{sha3} @tab ARMv8.2-A @tab No
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@tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies
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@code{fp}, @code{simd} and @code{sha2}.
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@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
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@tab Enable Advanced SIMD extensions. This implies @code{fp}.
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@item @code{sm4} @tab ARMv8.2-A @tab No
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@tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies
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@code{fp} and @code{simd}.
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@item @code{sme} @tab Armv9-A @tab No
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@tab Enable SME Extension.
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@item @code{sme-f64} @tab Armv9-A @tab No
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@tab Enable SME F64 Extension.
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@item @code{sme-i64} @tab Armv9-A @tab No
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@tab Enable SME I64 Extension.
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@item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
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@tab Enable Speculative Store Bypassing Safe state read and write.
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@item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later
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@tab Enable the Scalable Vector Extensions. This implies @code{fp16},
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@code{simd} and @code{compnum}.
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@item @code{sve2} @tab ARMv8-A @tab Armv9-A or later
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@tab Enable the SVE2 Extension. This implies @code{sve}.
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@item @code{sve2-aes} @tab ARMv8-A @tab No
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@tab Enable SVE2 AES Extension. This also enables the .Q->.B form of the
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@code{pmullt} and @code{pmullb} instructions. This implies @code{aes} and
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@code{sve2}.
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@item @code{sve2-bitperm} @tab ARMv8-A @tab No
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@tab Enable SVE2 BITPERM Extension.
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@item @code{sve2-sha3} @tab ARMv8-A @tab No
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@tab Enable SVE2 SHA3 Extension. This implies @code{sha3} and @code{sve2}.
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@item @code{sve2-sm4} @tab ARMv8-A @tab No
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@tab Enable SVE2 SM4 Extension. This implies @code{sm4} and @code{sve2}.
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@item @code{tme} @tab ARMv8-A @tab No
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@tab Enable Transactional Memory Extensions.
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@end multitable
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@node AArch64 Syntax
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@section Syntax
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@menu
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* AArch64-Chars:: Special Characters
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* AArch64-Regs:: Register Names
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* AArch64-Relocations:: Relocations
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@end menu
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@node AArch64-Chars
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@subsection Special Characters
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@cindex line comment character, AArch64
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@cindex AArch64 line comment character
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The presence of a @samp{//} on a line indicates the start of a comment
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that extends to the end of the current line. If a @samp{#} appears as
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the first character of a line, the whole line is treated as a comment.
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@cindex line separator, AArch64
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@cindex statement separator, AArch64
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@cindex AArch64 line separator
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The @samp{;} character can be used instead of a newline to separate
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statements.
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@cindex immediate character, AArch64
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@cindex AArch64 immediate character
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The @samp{#} can be optionally used to indicate immediate operands.
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@node AArch64-Regs
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@subsection Register Names
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@cindex AArch64 register names
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@cindex register names, AArch64
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Please refer to the section @samp{4.4 Register Names} of
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@samp{ARMv8 Instruction Set Overview}, which is available at
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@uref{http://infocenter.arm.com}.
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@node AArch64-Relocations
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@subsection Relocations
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@cindex relocations, AArch64
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@cindex AArch64 relocations
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@cindex MOVN, MOVZ and MOVK group relocations, AArch64
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Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
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by prefixing the label with @samp{#:abs_g2:} etc.
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For example to load the 48-bit absolute address of @var{foo} into x0:
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@smallexample
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movz x0, #:abs_g2:foo // bits 32-47, overflow check
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movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
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movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
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@end smallexample
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@cindex ADRP, ADD, LDR/STR group relocations, AArch64
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Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
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instructions can be generated by prefixing the label with
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@samp{:pg_hi21:} and @samp{#:lo12:} respectively.
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For example to use 33-bit (+/-4GB) pc-relative addressing to
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load the address of @var{foo} into x0:
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@smallexample
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adrp x0, :pg_hi21:foo
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add x0, x0, #:lo12:foo
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@end smallexample
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Or to load the value of @var{foo} into x0:
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@smallexample
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adrp x0, :pg_hi21:foo
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ldr x0, [x0, #:lo12:foo]
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@end smallexample
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Note that @samp{:pg_hi21:} is optional.
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@smallexample
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adrp x0, foo
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@end smallexample
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is equivalent to
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@smallexample
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adrp x0, :pg_hi21:foo
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@end smallexample
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@node AArch64 Floating Point
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@section Floating Point
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@cindex floating point, AArch64 (@sc{ieee})
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@cindex AArch64 floating point (@sc{ieee})
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The AArch64 architecture uses @sc{ieee} floating-point numbers.
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@node AArch64 Directives
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@section AArch64 Machine Directives
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@cindex machine directives, AArch64
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@cindex AArch64 machine directives
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@table @code
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@c AAAAAAAAAAAAAAAAAAAAAAAAA
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@cindex @code{.arch} directive, AArch64
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@item .arch @var{name}
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Select the target architecture. Valid values for @var{name} are the same as
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for the @option{-march} command-line option.
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Specifying @code{.arch} clears any previously selected architecture
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extensions.
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@cindex @code{.arch_extension} directive, AArch64
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@item .arch_extension @var{name}
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Add or remove an architecture extension to the target architecture. Valid
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values for @var{name} are the same as those accepted as architectural
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extensions by the @option{-mcpu} command-line option.
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@code{.arch_extension} may be used multiple times to add or remove extensions
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incrementally to the architecture being compiled for.
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@c BBBBBBBBBBBBBBBBBBBBBBBBBB
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@cindex @code{.bss} directive, AArch64
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@item .bss
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This directive switches to the @code{.bss} section.
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@c CCCCCCCCCCCCCCCCCCCCCCCCCC
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@cindex @code{.cpu} directive, AArch64
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@item .cpu @var{name}
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Set the target processor. Valid values for @var{name} are the same as
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those accepted by the @option{-mcpu=} command-line option.
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@c DDDDDDDDDDDDDDDDDDDDDDDDDD
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@cindex @code{.dword} directive, AArch64
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@item .dword @var{expressions}
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The @code{.dword} directive produces 64 bit values.
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@c EEEEEEEEEEEEEEEEEEEEEEEEEE
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@cindex @code{.even} directive, AArch64
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@item .even
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The @code{.even} directive aligns the output on the next even byte
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boundary.
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@c FFFFFFFFFFFFFFFFFFFFFFFFFF
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@cindex @code{.float16} directive, AArch64
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@item .float16 @var{value [,...,value_n]}
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Place the half precision floating point representation of one or more
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floating-point values into the current section.
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The format used to encode the floating point values is always the
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IEEE 754-2008 half precision floating point format.
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@c GGGGGGGGGGGGGGGGGGGGGGGGGG
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@c HHHHHHHHHHHHHHHHHHHHHHHHHH
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@c IIIIIIIIIIIIIIIIIIIIIIIIII
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@cindex @code{.inst} directive, AArch64
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@item .inst @var{expressions}
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Inserts the expressions into the output as if they were instructions,
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rather than data.
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@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
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@c KKKKKKKKKKKKKKKKKKKKKKKKKK
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@c LLLLLLLLLLLLLLLLLLLLLLLLLL
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@cindex @code{.ltorg} directive, AArch64
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@item .ltorg
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This directive causes the current contents of the literal pool to be
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dumped into the current section (which is assumed to be the .text
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section) at the current location (aligned to a word boundary).
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GAS maintains a separate literal pool for each section and each
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sub-section. The @code{.ltorg} directive will only affect the literal
|
|
pool of the current section and sub-section. At the end of assembly
|
|
all remaining, un-empty literal pools will automatically be dumped.
|
|
|
|
Note - older versions of GAS would dump the current literal
|
|
pool any time a section change occurred. This is no longer done, since
|
|
it prevents accurate control of the placement of literal pools.
|
|
|
|
@c MMMMMMMMMMMMMMMMMMMMMMMMMM
|
|
|
|
@c NNNNNNNNNNNNNNNNNNNNNNNNNN
|
|
@c OOOOOOOOOOOOOOOOOOOOOOOOOO
|
|
|
|
@c PPPPPPPPPPPPPPPPPPPPPPPPPP
|
|
|
|
@cindex @code{.pool} directive, AArch64
|
|
@item .pool
|
|
This is a synonym for .ltorg.
|
|
|
|
@c QQQQQQQQQQQQQQQQQQQQQQQQQQ
|
|
@c RRRRRRRRRRRRRRRRRRRRRRRRRR
|
|
|
|
@cindex @code{.req} directive, AArch64
|
|
@item @var{name} .req @var{register name}
|
|
This creates an alias for @var{register name} called @var{name}. For
|
|
example:
|
|
|
|
@smallexample
|
|
foo .req w0
|
|
@end smallexample
|
|
|
|
ip0, ip1, lr and fp are automatically defined to
|
|
alias to X16, X17, X30 and X29 respectively.
|
|
|
|
@c SSSSSSSSSSSSSSSSSSSSSSSSSS
|
|
|
|
@c TTTTTTTTTTTTTTTTTTTTTTTTTT
|
|
|
|
@cindex @code{.tlsdescadd} directive, AArch64
|
|
@item @code{.tlsdescadd}
|
|
Emits a TLSDESC_ADD reloc on the next instruction.
|
|
|
|
@cindex @code{.tlsdesccall} directive, AArch64
|
|
@item @code{.tlsdesccall}
|
|
Emits a TLSDESC_CALL reloc on the next instruction.
|
|
|
|
@cindex @code{.tlsdescldr} directive, AArch64
|
|
@item @code{.tlsdescldr}
|
|
Emits a TLSDESC_LDR reloc on the next instruction.
|
|
|
|
@c UUUUUUUUUUUUUUUUUUUUUUUUUU
|
|
|
|
@cindex @code{.unreq} directive, AArch64
|
|
@item .unreq @var{alias-name}
|
|
This undefines a register alias which was previously defined using the
|
|
@code{req} directive. For example:
|
|
|
|
@smallexample
|
|
foo .req w0
|
|
.unreq foo
|
|
@end smallexample
|
|
|
|
An error occurs if the name is undefined. Note - this pseudo op can
|
|
be used to delete builtin in register name aliases (eg 'w0'). This
|
|
should only be done if it is really necessary.
|
|
|
|
@c VVVVVVVVVVVVVVVVVVVVVVVVVV
|
|
|
|
@cindex @code{.variant_pcs} directive, AArch64
|
|
@item .variant_pcs @var{symbol}
|
|
This directive marks @var{symbol} referencing a function that may
|
|
follow a variant procedure call standard with different register
|
|
usage convention from the base procedure call standard.
|
|
|
|
@c WWWWWWWWWWWWWWWWWWWWWWWWWW
|
|
@c XXXXXXXXXXXXXXXXXXXXXXXXXX
|
|
|
|
@cindex @code{.xword} directive, AArch64
|
|
@item .xword @var{expressions}
|
|
The @code{.xword} directive produces 64 bit values. This is the same
|
|
as the @code{.dword} directive.
|
|
|
|
@c YYYYYYYYYYYYYYYYYYYYYYYYYY
|
|
@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
|
|
|
|
@cindex @code{.cfi_b_key_frame} directive, AArch64
|
|
@item @code{.cfi_b_key_frame}
|
|
The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
|
|
corresponding to the current frame's FDE, meaning that its return address has
|
|
been signed with the B-key. If two frames are signed with differing keys then
|
|
they will not share the same CIE. This information is intended to be used by
|
|
the stack unwinder in order to properly authenticate return addresses.
|
|
|
|
@end table
|
|
|
|
@node AArch64 Opcodes
|
|
@section Opcodes
|
|
|
|
@cindex AArch64 opcodes
|
|
@cindex opcodes for AArch64
|
|
GAS implements all the standard AArch64 opcodes. It also
|
|
implements several pseudo opcodes, including several synthetic load
|
|
instructions.
|
|
|
|
@table @code
|
|
|
|
@cindex @code{LDR reg,=<expr>} pseudo op, AArch64
|
|
@item LDR =
|
|
@smallexample
|
|
ldr <register> , =<expression>
|
|
@end smallexample
|
|
|
|
The constant expression will be placed into the nearest literal pool (if it not
|
|
already there) and a PC-relative LDR instruction will be generated.
|
|
|
|
@end table
|
|
|
|
For more information on the AArch64 instruction set and assembly language
|
|
notation, see @samp{ARMv8 Instruction Set Overview} available at
|
|
@uref{http://infocenter.arm.com}.
|
|
|
|
|
|
@node AArch64 Mapping Symbols
|
|
@section Mapping Symbols
|
|
|
|
The AArch64 ELF specification requires that special symbols be inserted
|
|
into object files to mark certain features:
|
|
|
|
@table @code
|
|
|
|
@cindex @code{$x}
|
|
@item $x
|
|
At the start of a region of code containing AArch64 instructions.
|
|
|
|
@cindex @code{$d}
|
|
@item $d
|
|
At the start of a region of data.
|
|
|
|
@end table
|