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https://sourceware.org/git/binutils-gdb.git
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405feb71d4
Fix typos in comments. NFC. Tested on x86_64-linux. gdb/ChangeLog: 2019-10-17 Tom de Vries <tdevries@suse.de> * arm-nbsd-nat.c: Fix typos in comments. * arm-tdep.c: Same. * darwin-nat-info.c: Same. * dwarf2read.c: Same. * elfread.c: Same. * event-top.c: Same. * findvar.c: Same. * gdbtypes.c: Same. * hppa-tdep.c: Same. * i386-tdep.c: Same. * jit.c: Same. * main.c: Same. * mdebugread.c: Same. * moxie-tdep.c: Same. * nto-procfs.c: Same. * osabi.c: Same. * ppc-linux-tdep.c: Same. * remote.c: Same. * riscv-tdep.c: Same. * s390-tdep.c: Same. * sh-tdep.c: Same. * sparc-linux-tdep.c: Same. * sparc-nat.c: Same. * stack.c: Same. * target-descriptions.c: Same. * top.c: Same. * varobj.c: Same. Change-Id: I6047967abd2d51c9000dea15184d19f4e952c3ff
454 lines
11 KiB
C
454 lines
11 KiB
C
/* Native-dependent code for BSD Unix running on ARM's, for GDB.
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Copyright (C) 1988-2019 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "gdbcore.h"
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#include "inferior.h"
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#include "regcache.h"
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#include "target.h"
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#include <sys/types.h>
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#include <sys/ptrace.h>
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#include <machine/reg.h>
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#include <machine/frame.h>
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#include "arm-tdep.h"
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#include "inf-ptrace.h"
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class arm_netbsd_nat_target final : public inf_ptrace_target
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{
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public:
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/* Add our register access methods. */
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void fetch_registers (struct regcache *, int) override;
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void store_registers (struct regcache *, int) override;
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};
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static arm_netbsd_nat_target the_arm_netbsd_nat_target;
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static void
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arm_supply_gregset (struct regcache *regcache, struct reg *gregset)
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{
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int regno;
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CORE_ADDR r_pc;
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/* Integer registers. */
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for (regno = ARM_A1_REGNUM; regno < ARM_SP_REGNUM; regno++)
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regcache->raw_supply (regno, (char *) &gregset->r[regno]);
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regcache->raw_supply (ARM_SP_REGNUM, (char *) &gregset->r_sp);
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regcache->raw_supply (ARM_LR_REGNUM, (char *) &gregset->r_lr);
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/* This is ok: we're running native... */
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r_pc = gdbarch_addr_bits_remove (regcache->arch (), gregset->r_pc);
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regcache->raw_supply (ARM_PC_REGNUM, (char *) &r_pc);
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if (arm_apcs_32)
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regcache->raw_supply (ARM_PS_REGNUM, (char *) &gregset->r_cpsr);
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else
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regcache->raw_supply (ARM_PS_REGNUM, (char *) &gregset->r_pc);
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}
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static void
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arm_supply_fparegset (struct regcache *regcache, struct fpreg *fparegset)
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{
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int regno;
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for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++)
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regcache->raw_supply (regno,
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(char *) &fparegset->fpr[regno - ARM_F0_REGNUM]);
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regcache->raw_supply (ARM_FPS_REGNUM, (char *) &fparegset->fpr_fpsr);
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}
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static void
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fetch_register (struct regcache *regcache, int regno)
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{
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struct reg inferior_registers;
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int ret;
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ret = ptrace (PT_GETREGS, regcache->ptid ().pid (),
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(PTRACE_TYPE_ARG3) &inferior_registers, 0);
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if (ret < 0)
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{
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warning (_("unable to fetch general register"));
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return;
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}
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switch (regno)
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{
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case ARM_SP_REGNUM:
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regcache->raw_supply (ARM_SP_REGNUM, (char *) &inferior_registers.r_sp);
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break;
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case ARM_LR_REGNUM:
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regcache->raw_supply (ARM_LR_REGNUM, (char *) &inferior_registers.r_lr);
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break;
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case ARM_PC_REGNUM:
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/* This is ok: we're running native... */
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inferior_registers.r_pc = gdbarch_addr_bits_remove
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(regcache->arch (),
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inferior_registers.r_pc);
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regcache->raw_supply (ARM_PC_REGNUM, (char *) &inferior_registers.r_pc);
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break;
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case ARM_PS_REGNUM:
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if (arm_apcs_32)
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regcache->raw_supply (ARM_PS_REGNUM,
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(char *) &inferior_registers.r_cpsr);
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else
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regcache->raw_supply (ARM_PS_REGNUM,
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(char *) &inferior_registers.r_pc);
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break;
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default:
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regcache->raw_supply (regno, (char *) &inferior_registers.r[regno]);
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break;
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}
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}
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static void
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fetch_regs (struct regcache *regcache)
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{
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struct reg inferior_registers;
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int ret;
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int regno;
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ret = ptrace (PT_GETREGS, regcache->ptid ().pid (),
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(PTRACE_TYPE_ARG3) &inferior_registers, 0);
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if (ret < 0)
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{
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warning (_("unable to fetch general registers"));
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return;
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}
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arm_supply_gregset (regcache, &inferior_registers);
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}
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static void
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fetch_fp_register (struct regcache *regcache, int regno)
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{
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struct fpreg inferior_fp_registers;
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int ret;
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ret = ptrace (PT_GETFPREGS, regcache->ptid ().pid (),
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(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);
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if (ret < 0)
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{
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warning (_("unable to fetch floating-point register"));
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return;
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}
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switch (regno)
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{
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case ARM_FPS_REGNUM:
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regcache->raw_supply (ARM_FPS_REGNUM,
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(char *) &inferior_fp_registers.fpr_fpsr);
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break;
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default:
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regcache->raw_supply
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(regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]);
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break;
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}
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}
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static void
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fetch_fp_regs (struct regcache *regcache)
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{
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struct fpreg inferior_fp_registers;
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int ret;
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int regno;
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ret = ptrace (PT_GETFPREGS, regcache->ptid ().pid (),
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(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);
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if (ret < 0)
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{
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warning (_("unable to fetch general registers"));
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return;
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}
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arm_supply_fparegset (regcache, &inferior_fp_registers);
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}
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void
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arm_nbsd_nat_target::fetch_registers (struct regcache *regcache, int regno)
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{
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if (regno >= 0)
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{
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if (regno < ARM_F0_REGNUM || regno > ARM_FPS_REGNUM)
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fetch_register (regcache, regno);
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else
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fetch_fp_register (regcache, regno);
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}
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else
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{
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fetch_regs (regcache);
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fetch_fp_regs (regcache);
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}
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}
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static void
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store_register (const struct regcache *regcache, int regno)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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struct reg inferior_registers;
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int ret;
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ret = ptrace (PT_GETREGS, regcache->ptid ().pid (),
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(PTRACE_TYPE_ARG3) &inferior_registers, 0);
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if (ret < 0)
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{
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warning (_("unable to fetch general registers"));
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return;
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}
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switch (regno)
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{
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case ARM_SP_REGNUM:
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regcache->raw_collect (ARM_SP_REGNUM, (char *) &inferior_registers.r_sp);
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break;
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case ARM_LR_REGNUM:
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regcache->raw_collect (ARM_LR_REGNUM, (char *) &inferior_registers.r_lr);
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break;
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case ARM_PC_REGNUM:
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if (arm_apcs_32)
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regcache->raw_collect (ARM_PC_REGNUM,
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(char *) &inferior_registers.r_pc);
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else
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{
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unsigned pc_val;
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regcache->raw_collect (ARM_PC_REGNUM, (char *) &pc_val);
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pc_val = gdbarch_addr_bits_remove (gdbarch, pc_val);
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inferior_registers.r_pc ^= gdbarch_addr_bits_remove
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(gdbarch, inferior_registers.r_pc);
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inferior_registers.r_pc |= pc_val;
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}
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break;
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case ARM_PS_REGNUM:
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if (arm_apcs_32)
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regcache->raw_collect (ARM_PS_REGNUM,
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(char *) &inferior_registers.r_cpsr);
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else
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{
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unsigned psr_val;
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regcache->raw_collect (ARM_PS_REGNUM, (char *) &psr_val);
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psr_val ^= gdbarch_addr_bits_remove (gdbarch, psr_val);
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inferior_registers.r_pc = gdbarch_addr_bits_remove
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(gdbarch, inferior_registers.r_pc);
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inferior_registers.r_pc |= psr_val;
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}
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break;
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default:
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regcache->raw_collect (regno, (char *) &inferior_registers.r[regno]);
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break;
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}
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ret = ptrace (PT_SETREGS, regcache->ptid ().pid (),
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(PTRACE_TYPE_ARG3) &inferior_registers, 0);
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if (ret < 0)
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warning (_("unable to write register %d to inferior"), regno);
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}
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static void
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store_regs (const struct regcache *regcache)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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struct reg inferior_registers;
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int ret;
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int regno;
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for (regno = ARM_A1_REGNUM; regno < ARM_SP_REGNUM; regno++)
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regcache->raw_collect (regno, (char *) &inferior_registers.r[regno]);
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regcache->raw_collect (ARM_SP_REGNUM, (char *) &inferior_registers.r_sp);
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regcache->raw_collect (ARM_LR_REGNUM, (char *) &inferior_registers.r_lr);
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if (arm_apcs_32)
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{
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regcache->raw_collect (ARM_PC_REGNUM, (char *) &inferior_registers.r_pc);
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regcache->raw_collect (ARM_PS_REGNUM,
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(char *) &inferior_registers.r_cpsr);
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}
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else
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{
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unsigned pc_val;
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unsigned psr_val;
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regcache->raw_collect (ARM_PC_REGNUM, (char *) &pc_val);
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regcache->raw_collect (ARM_PS_REGNUM, (char *) &psr_val);
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pc_val = gdbarch_addr_bits_remove (gdbarch, pc_val);
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psr_val ^= gdbarch_addr_bits_remove (gdbarch, psr_val);
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inferior_registers.r_pc = pc_val | psr_val;
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}
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ret = ptrace (PT_SETREGS, regcache->ptid ().pid (),
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(PTRACE_TYPE_ARG3) &inferior_registers, 0);
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if (ret < 0)
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warning (_("unable to store general registers"));
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}
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static void
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store_fp_register (const struct regcache *regcache, int regno)
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{
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struct fpreg inferior_fp_registers;
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int ret;
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ret = ptrace (PT_GETFPREGS, regcache->ptid ().pid (),
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(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);
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if (ret < 0)
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{
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warning (_("unable to fetch floating-point registers"));
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return;
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}
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switch (regno)
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{
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case ARM_FPS_REGNUM:
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regcache->raw_collect (ARM_FPS_REGNUM,
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(char *) &inferior_fp_registers.fpr_fpsr);
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break;
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default:
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regcache->raw_collect
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(regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]);
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break;
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}
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ret = ptrace (PT_SETFPREGS, regcache->ptid ().pid (),
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(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);
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if (ret < 0)
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warning (_("unable to write register %d to inferior"), regno);
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}
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static void
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store_fp_regs (const struct regcache *regcache)
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{
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struct fpreg inferior_fp_registers;
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int ret;
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int regno;
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for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++)
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regcache->raw_collect
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(regno, (char *) &inferior_fp_registers.fpr[regno - ARM_F0_REGNUM]);
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regcache->raw_collect (ARM_FPS_REGNUM,
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(char *) &inferior_fp_registers.fpr_fpsr);
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ret = ptrace (PT_SETFPREGS, regcache->ptid ().pid (),
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(PTRACE_TYPE_ARG3) &inferior_fp_registers, 0);
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if (ret < 0)
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warning (_("unable to store floating-point registers"));
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}
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void
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arm_nbsd_nat_target::store_registers (struct regcache *regcache, int regno)
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{
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if (regno >= 0)
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{
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if (regno < ARM_F0_REGNUM || regno > ARM_FPS_REGNUM)
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store_register (regcache, regno);
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else
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store_fp_register (regcache, regno);
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}
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else
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{
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store_regs (regcache);
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store_fp_regs (regcache);
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}
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}
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static void
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fetch_elfcore_registers (struct regcache *regcache,
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char *core_reg_sect, unsigned core_reg_size,
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int which, CORE_ADDR ignore)
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{
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struct reg gregset;
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struct fpreg fparegset;
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switch (which)
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{
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case 0: /* Integer registers. */
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if (core_reg_size != sizeof (struct reg))
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warning (_("wrong size of register set in core file"));
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else
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{
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/* The memcpy may be unnecessary, but we can't really be sure
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of the alignment of the data in the core file. */
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memcpy (&gregset, core_reg_sect, sizeof (gregset));
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arm_supply_gregset (regcache, &gregset);
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}
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break;
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case 2:
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if (core_reg_size != sizeof (struct fpreg))
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warning (_("wrong size of FPA register set in core file"));
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else
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{
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/* The memcpy may be unnecessary, but we can't really be sure
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of the alignment of the data in the core file. */
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memcpy (&fparegset, core_reg_sect, sizeof (fparegset));
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arm_supply_fparegset (regcache, &fparegset);
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}
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break;
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default:
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/* Don't know what kind of register request this is; just ignore it. */
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break;
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}
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}
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static struct core_fns arm_netbsd_elfcore_fns =
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{
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bfd_target_elf_flavour, /* core_flavour. */
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default_check_format, /* check_format. */
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default_core_sniffer, /* core_sniffer. */
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fetch_elfcore_registers, /* core_read_registers. */
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NULL
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};
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void
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_initialize_arm_netbsd_nat (void)
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{
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add_inf_child_target (&the_arm_netbsd_nat_target);
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deprecated_add_core_fns (&arm_netbsd_elfcore_fns);
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}
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