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9ed608f98b
The Statistical Profile Extension adds the instruction PSB CSYNC as an alias for the HINT #17 instruction. This patch adds support for aliases of HINT which take an operand, adding a table to store operand names and their matching hint number as well as encoding and decoding functions for such operands. Parsing and printing the operands are deferred to any support added for aliases with such operands. include/opcode/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64.h (aarch64_hint_options): Declare. (aarch64_opnd_info): Add field hint_option. opcodes/ 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm.c (aarch64_ins_hint): New. * aarch64-asm.h (aarch64_ins_hint): Declare. * aarch64-dis.c (aarch64_ext_hint): New. * aarch64-dis.h (aarch64_ext_hint): Declare. * aarch64-opc-2.c: Regenerate. * aarch64-opc.c (aarch64_hint_options): New. * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos. Change-Id: I2205038fc1c47d3025d1f0bc2fbf405b5575b287
75 lines
2.7 KiB
C
75 lines
2.7 KiB
C
/* aarch64-asm.h -- Header file for aarch64-asm.c and aarch64-asm-2.c.
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Copyright (C) 2012-2015 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef OPCODES_AARCH64_ASM_H
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#define OPCODES_AARCH64_ASM_H
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#include "aarch64-opc.h"
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/* Given OPCODE, return the opcode entry that OPCODE aliases to, e.g.
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given LSL, return UBFM. */
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const aarch64_opcode* aarch64_find_real_opcode (const aarch64_opcode *);
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/* Switch-table-based high-level operand inserter. */
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const char* aarch64_insert_operand (const aarch64_operand *,
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const aarch64_opnd_info *, aarch64_insn *,
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const aarch64_inst *);
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/* Operand inserters. */
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#define AARCH64_DECL_OPD_INSERTER(x) \
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const char* aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \
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aarch64_insn *, const aarch64_inst *)
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AARCH64_DECL_OPD_INSERTER (ins_regno);
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AARCH64_DECL_OPD_INSERTER (ins_reglane);
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AARCH64_DECL_OPD_INSERTER (ins_reglist);
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AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist);
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AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist_r);
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AARCH64_DECL_OPD_INSERTER (ins_ldst_elemlist);
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AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_shift);
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AARCH64_DECL_OPD_INSERTER (ins_imm);
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AARCH64_DECL_OPD_INSERTER (ins_imm_half);
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AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_modified);
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AARCH64_DECL_OPD_INSERTER (ins_fbits);
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AARCH64_DECL_OPD_INSERTER (ins_aimm);
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AARCH64_DECL_OPD_INSERTER (ins_limm);
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AARCH64_DECL_OPD_INSERTER (ins_ft);
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AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
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AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
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AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
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AARCH64_DECL_OPD_INSERTER (ins_addr_uimm12);
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AARCH64_DECL_OPD_INSERTER (ins_simd_addr_post);
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AARCH64_DECL_OPD_INSERTER (ins_cond);
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AARCH64_DECL_OPD_INSERTER (ins_sysreg);
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AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
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AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
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AARCH64_DECL_OPD_INSERTER (ins_barrier);
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AARCH64_DECL_OPD_INSERTER (ins_hint);
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AARCH64_DECL_OPD_INSERTER (ins_prfop);
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AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
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AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);
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#undef AARCH64_DECL_OPD_INSERTER
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#endif /* OPCODES_AARCH64_ASM_H */
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