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f9a4d54332
The m4 macro has 2 args: the "wire" settings (which represents the hardwired port behavior), and the default settings (which are used if nothing else is specified). If none are specified, the arch is expected to support both, and the value will be probed based on the user runtime options or the input program. Only two arches today set the default value (bpf & mips). We can probably let this go as it only shows up in one scenario: the sim is invoked, but with no inputs, and no user endian selection. This means bpf will not behave like the other arches: an error is shown and forces the user to make a choice. If an input program is used though, we'll still switch the default to that. This allows us to remove the WITH_DEFAULT_TARGET_BYTE_ORDER setting. For the ports that set a "wire" endian, move it to the runtime init of the respective sim_open calls. This allows us to change the WITH_TARGET_BYTE_ORDER to purely a user-selected configure setting if they want to force a specific endianness. With all the endian logic moved to runtime selection, we can move the configure call up to the common dir so we only process it once across all ports. The ppc arch was picking the wire endian based on the target used, but since we weren't doing that for other biendian arches, we can let this go too. We'll rely on the input selecting the endian, or make the user decide.
653 lines
16 KiB
C
653 lines
16 KiB
C
/* interp.c -- Simulator for Motorola 68HC11/68HC12
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Copyright (C) 1999-2021 Free Software Foundation, Inc.
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Written by Stephane Carrez (stcarrez@nerim.fr)
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#include "sim-main.h"
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#include "sim-assert.h"
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#include "sim-hw.h"
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#include "sim-options.h"
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#include "hw-tree.h"
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#include "hw-device.h"
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#include "hw-ports.h"
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#include "elf32-m68hc1x.h"
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#ifndef MONITOR_BASE
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# define MONITOR_BASE (0x0C000)
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# define MONITOR_SIZE (0x04000)
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#endif
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static void sim_get_info (SIM_DESC sd, char *cmd);
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struct sim_info_list
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{
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const char *name;
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const char *device;
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};
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struct sim_info_list dev_list_68hc11[] = {
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{"cpu", "/m68hc11"},
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{"timer", "/m68hc11/m68hc11tim"},
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{"sio", "/m68hc11/m68hc11sio"},
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{"spi", "/m68hc11/m68hc11spi"},
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{"eeprom", "/m68hc11/m68hc11eepr"},
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{0, 0}
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};
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struct sim_info_list dev_list_68hc12[] = {
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{"cpu", "/m68hc12"},
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{"timer", "/m68hc12/m68hc12tim"},
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{"sio", "/m68hc12/m68hc12sio"},
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{"spi", "/m68hc12/m68hc12spi"},
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{"eeprom", "/m68hc12/m68hc12eepr"},
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{0, 0}
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};
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/* Cover function of sim_state_free to free the cpu buffers as well. */
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static void
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free_state (SIM_DESC sd)
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{
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if (STATE_MODULES (sd) != NULL)
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sim_module_uninstall (sd);
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sim_state_free (sd);
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}
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/* Give some information about the simulator. */
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static void
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sim_get_info (SIM_DESC sd, char *cmd)
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{
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sim_cpu *cpu;
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cpu = STATE_CPU (sd, 0);
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if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-'))
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{
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int i;
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struct hw *hw_dev;
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struct sim_info_list *dev_list;
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const struct bfd_arch_info *arch;
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arch = STATE_ARCHITECTURE (sd);
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cmd++;
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if (arch->arch == bfd_arch_m68hc11)
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dev_list = dev_list_68hc11;
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else
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dev_list = dev_list_68hc12;
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for (i = 0; dev_list[i].name; i++)
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if (strcmp (cmd, dev_list[i].name) == 0)
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break;
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if (dev_list[i].name == 0)
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{
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sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
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sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
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return;
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}
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hw_dev = sim_hw_parse (sd, "%s", dev_list[i].device);
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if (hw_dev == 0)
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{
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sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
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return;
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}
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hw_ioctl (hw_dev, 23, 0);
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return;
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}
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cpu_info (sd, cpu);
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interrupts_info (sd, &cpu->cpu_interrupts);
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}
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void
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sim_board_reset (SIM_DESC sd)
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{
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struct hw *hw_cpu;
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sim_cpu *cpu;
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const struct bfd_arch_info *arch;
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const char *cpu_type;
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cpu = STATE_CPU (sd, 0);
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arch = STATE_ARCHITECTURE (sd);
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/* hw_cpu = sim_hw_parse (sd, "/"); */
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if (arch->arch == bfd_arch_m68hc11)
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{
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cpu->cpu_type = CPU_M6811;
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cpu_type = "/m68hc11";
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}
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else
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{
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cpu->cpu_type = CPU_M6812;
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cpu_type = "/m68hc12";
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}
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hw_cpu = sim_hw_parse (sd, "%s", cpu_type);
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if (hw_cpu == 0)
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{
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sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
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return;
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}
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cpu_reset (cpu);
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hw_port_event (hw_cpu, 3, 0);
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cpu_restart (cpu);
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}
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static int
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sim_hw_configure (SIM_DESC sd)
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{
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const struct bfd_arch_info *arch;
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struct hw *device_tree;
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sim_cpu *cpu;
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arch = STATE_ARCHITECTURE (sd);
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if (arch == 0)
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return 0;
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cpu = STATE_CPU (sd, 0);
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cpu->cpu_configured_arch = arch;
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device_tree = sim_hw_parse (sd, "/");
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if (arch->arch == bfd_arch_m68hc11)
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{
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cpu->cpu_interpretor = cpu_interp_m6811;
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if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
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{
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/* Allocate core managed memory */
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/* the monitor */
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sim_do_commandf (sd, "memory region 0x%x@%d,0x%x",
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/* MONITOR_BASE, MONITOR_SIZE */
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0x8000, M6811_RAM_LEVEL, 0x8000);
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sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
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M6811_RAM_LEVEL);
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sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
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if (cpu->bank_start < cpu->bank_end)
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{
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sim_do_commandf (sd, "memory region 0x%x@%d,0x100000",
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cpu->bank_virtual, M6811_RAM_LEVEL);
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sim_hw_parse (sd, "/m68hc11/use_bank 1");
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}
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}
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if (cpu->cpu_start_mode)
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{
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sim_hw_parse (sd, "/m68hc11/mode %s", cpu->cpu_start_mode);
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}
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if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
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{
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sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
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sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
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sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
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}
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if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
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{
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/* M68hc11 Timer configuration. */
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sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
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sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
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sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
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}
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/* Create the SPI device. */
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if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
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{
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sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
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sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
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}
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if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
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{
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/* M68hc11 persistent ram configuration. */
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sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
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sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
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sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
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/*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */
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}
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if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
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{
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sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
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sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
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}
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sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
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sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
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sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
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sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
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cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
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}
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else
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{
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cpu->cpu_interpretor = cpu_interp_m6812;
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if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
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{
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/* Allocate core external memory. */
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sim_do_commandf (sd, "memory region 0x%x@%d,0x%x",
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0x8000, M6811_RAM_LEVEL, 0x8000);
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sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
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M6811_RAM_LEVEL);
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if (cpu->bank_start < cpu->bank_end)
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{
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sim_do_commandf (sd, "memory region 0x%x@%d,0x100000",
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cpu->bank_virtual, M6811_RAM_LEVEL);
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sim_hw_parse (sd, "/m68hc12/use_bank 1");
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}
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sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
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}
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if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
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{
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sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
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sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
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sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
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}
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if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
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{
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/* M68hc11 Timer configuration. */
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sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
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sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
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sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
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}
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/* Create the SPI device. */
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if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
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{
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sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
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sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
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}
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if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
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{
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/* M68hc11 persistent ram configuration. */
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sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
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sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
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sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
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}
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if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
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{
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sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
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sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
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}
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sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
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sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
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sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
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sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
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cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
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}
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return 1;
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}
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/* Get the memory bank parameters by looking at the global symbols
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defined by the linker. */
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static int
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sim_get_bank_parameters (SIM_DESC sd)
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{
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sim_cpu *cpu;
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unsigned size;
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bfd_vma addr;
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cpu = STATE_CPU (sd, 0);
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addr = trace_sym_value (sd, BFD_M68HC11_BANK_START_NAME);
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if (addr != -1)
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cpu->bank_start = addr;
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size = trace_sym_value (sd, BFD_M68HC11_BANK_SIZE_NAME);
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if (size == -1)
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size = 0;
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addr = trace_sym_value (sd, BFD_M68HC11_BANK_VIRTUAL_NAME);
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if (addr != -1)
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cpu->bank_virtual = addr;
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cpu->bank_end = cpu->bank_start + size;
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cpu->bank_shift = 0;
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for (; size > 1; size >>= 1)
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cpu->bank_shift++;
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return 0;
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}
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static int
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sim_prepare_for_program (SIM_DESC sd, bfd* abfd)
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{
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sim_cpu *cpu;
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int elf_flags = 0;
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cpu = STATE_CPU (sd, 0);
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if (abfd != NULL)
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{
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asection *s;
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if (bfd_get_flavour (abfd) == bfd_target_elf_flavour)
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elf_flags = elf_elfheader (abfd)->e_flags;
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cpu->cpu_elf_start = bfd_get_start_address (abfd);
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/* See if any section sets the reset address */
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cpu->cpu_use_elf_start = 1;
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for (s = abfd->sections; s && cpu->cpu_use_elf_start; s = s->next)
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{
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if (s->flags & SEC_LOAD)
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{
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bfd_size_type size;
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size = bfd_section_size (s);
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if (size > 0)
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{
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bfd_vma lma;
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if (STATE_LOAD_AT_LMA_P (sd))
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lma = bfd_section_lma (s);
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else
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lma = bfd_section_vma (s);
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if (lma <= 0xFFFE && lma+size >= 0x10000)
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cpu->cpu_use_elf_start = 0;
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}
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}
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}
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if (elf_flags & E_M68HC12_BANKS)
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{
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if (sim_get_bank_parameters (sd) != 0)
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sim_io_eprintf (sd, "Memory bank parameters are not initialized\n");
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}
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}
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if (!sim_hw_configure (sd))
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return SIM_RC_FAIL;
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/* reset all state information */
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sim_board_reset (sd);
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return SIM_RC_OK;
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}
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static sim_cia
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m68hc11_pc_get (sim_cpu *cpu)
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{
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return cpu_get_pc (cpu);
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}
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static void
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m68hc11_pc_set (sim_cpu *cpu, sim_cia pc)
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{
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cpu_set_pc (cpu, pc);
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}
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static int m68hc11_reg_fetch (SIM_CPU *, int, unsigned char *, int);
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static int m68hc11_reg_store (SIM_CPU *, int, unsigned char *, int);
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SIM_DESC
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sim_open (SIM_OPEN_KIND kind, host_callback *callback,
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bfd *abfd, char * const *argv)
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{
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int i;
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SIM_DESC sd;
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sim_cpu *cpu;
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sd = sim_state_alloc (kind, callback);
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SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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/* Set default options before parsing user options. */
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current_target_byte_order = BFD_ENDIAN_BIG;
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/* The cpu data is kept in a separately allocated chunk of memory. */
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if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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cpu = STATE_CPU (sd, 0);
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cpu_initialize (sd, cpu);
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if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* The parser will print an error message for us, so we silently return. */
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if (sim_parse_args (sd, argv) != SIM_RC_OK)
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{
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/* Uninstall the modules to avoid memory leaks,
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file descriptor leaks, etc. */
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free_state (sd);
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return 0;
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}
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/* Check for/establish the a reference program image. */
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if (sim_analyze_program (sd,
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(STATE_PROG_ARGV (sd) != NULL
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? *STATE_PROG_ARGV (sd)
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: NULL), abfd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Establish any remaining configuration options. */
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if (sim_config (sd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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if (sim_post_argv_init (sd) != SIM_RC_OK)
|
|
{
|
|
/* Uninstall the modules to avoid memory leaks,
|
|
file descriptor leaks, etc. */
|
|
free_state (sd);
|
|
return 0;
|
|
}
|
|
if (sim_prepare_for_program (sd, abfd) != SIM_RC_OK)
|
|
{
|
|
free_state (sd);
|
|
return 0;
|
|
}
|
|
|
|
/* CPU specific initialization. */
|
|
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
|
|
{
|
|
SIM_CPU *cpu = STATE_CPU (sd, i);
|
|
|
|
CPU_REG_FETCH (cpu) = m68hc11_reg_fetch;
|
|
CPU_REG_STORE (cpu) = m68hc11_reg_store;
|
|
CPU_PC_FETCH (cpu) = m68hc11_pc_get;
|
|
CPU_PC_STORE (cpu) = m68hc11_pc_set;
|
|
}
|
|
|
|
return sd;
|
|
}
|
|
|
|
/* Generic implementation of sim_engine_run that works within the
|
|
sim_engine setjmp/longjmp framework. */
|
|
|
|
void
|
|
sim_engine_run (SIM_DESC sd,
|
|
int next_cpu_nr, /* ignore */
|
|
int nr_cpus, /* ignore */
|
|
int siggnal) /* ignore */
|
|
{
|
|
sim_cpu *cpu;
|
|
|
|
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
|
|
cpu = STATE_CPU (sd, 0);
|
|
while (1)
|
|
{
|
|
cpu_single_step (cpu);
|
|
|
|
/* process any events */
|
|
if (sim_events_tickn (sd, cpu->cpu_current_cycle))
|
|
{
|
|
sim_events_process (sd);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
sim_info (SIM_DESC sd, int verbose)
|
|
{
|
|
const char *cpu_type;
|
|
const struct bfd_arch_info *arch;
|
|
|
|
/* Nothing to do if there is no verbose flag set. */
|
|
if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
|
|
return;
|
|
|
|
arch = STATE_ARCHITECTURE (sd);
|
|
if (arch->arch == bfd_arch_m68hc11)
|
|
cpu_type = "68HC11";
|
|
else
|
|
cpu_type = "68HC12";
|
|
|
|
sim_io_eprintf (sd, "Simulator info:\n");
|
|
sim_io_eprintf (sd, " CPU Motorola %s\n", cpu_type);
|
|
sim_get_info (sd, 0);
|
|
sim_module_info (sd, verbose || STATE_VERBOSE_P (sd));
|
|
}
|
|
|
|
SIM_RC
|
|
sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
|
|
char * const *argv, char * const *env)
|
|
{
|
|
return sim_prepare_for_program (sd, abfd);
|
|
}
|
|
|
|
static int
|
|
m68hc11_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
|
|
{
|
|
uint16 val;
|
|
int size = 2;
|
|
|
|
switch (rn)
|
|
{
|
|
case A_REGNUM:
|
|
val = cpu_get_a (cpu);
|
|
size = 1;
|
|
break;
|
|
|
|
case B_REGNUM:
|
|
val = cpu_get_b (cpu);
|
|
size = 1;
|
|
break;
|
|
|
|
case D_REGNUM:
|
|
val = cpu_get_d (cpu);
|
|
break;
|
|
|
|
case X_REGNUM:
|
|
val = cpu_get_x (cpu);
|
|
break;
|
|
|
|
case Y_REGNUM:
|
|
val = cpu_get_y (cpu);
|
|
break;
|
|
|
|
case SP_REGNUM:
|
|
val = cpu_get_sp (cpu);
|
|
break;
|
|
|
|
case PC_REGNUM:
|
|
val = cpu_get_pc (cpu);
|
|
break;
|
|
|
|
case PSW_REGNUM:
|
|
val = cpu_get_ccr (cpu);
|
|
size = 1;
|
|
break;
|
|
|
|
case PAGE_REGNUM:
|
|
val = cpu_get_page (cpu);
|
|
size = 1;
|
|
break;
|
|
|
|
default:
|
|
val = 0;
|
|
break;
|
|
}
|
|
if (size == 1)
|
|
{
|
|
memory[0] = val;
|
|
}
|
|
else
|
|
{
|
|
memory[0] = val >> 8;
|
|
memory[1] = val & 0x0FF;
|
|
}
|
|
return size;
|
|
}
|
|
|
|
static int
|
|
m68hc11_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
|
|
{
|
|
uint16 val;
|
|
|
|
val = *memory++;
|
|
if (length == 2)
|
|
val = (val << 8) | *memory;
|
|
|
|
switch (rn)
|
|
{
|
|
case D_REGNUM:
|
|
cpu_set_d (cpu, val);
|
|
break;
|
|
|
|
case A_REGNUM:
|
|
cpu_set_a (cpu, val);
|
|
return 1;
|
|
|
|
case B_REGNUM:
|
|
cpu_set_b (cpu, val);
|
|
return 1;
|
|
|
|
case X_REGNUM:
|
|
cpu_set_x (cpu, val);
|
|
break;
|
|
|
|
case Y_REGNUM:
|
|
cpu_set_y (cpu, val);
|
|
break;
|
|
|
|
case SP_REGNUM:
|
|
cpu_set_sp (cpu, val);
|
|
break;
|
|
|
|
case PC_REGNUM:
|
|
cpu_set_pc (cpu, val);
|
|
break;
|
|
|
|
case PSW_REGNUM:
|
|
cpu_set_ccr (cpu, val);
|
|
return 1;
|
|
|
|
case PAGE_REGNUM:
|
|
cpu_set_page (cpu, val);
|
|
return 1;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return 2;
|
|
}
|