mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-21 04:42:53 +08:00
b83b4b1382
This patch enables the new Transactional Memory Extension added recently as part of Arm's new architecture technologies. We introduce a new optional extension "tme" to enable this. The following instructions are part of the extension: * tstart <Xt> * ttest <Xt> * tcommit * tcancel #<imm> The ISA for the above can be found here: https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order *** gas/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_features): Add "tme". * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/tme-invalid.d: New test. * testsuite/gas/aarch64/tme-invalid.l: New test. * testsuite/gas/aarch64/tme-invalid.s: New test. * testsuite/gas/aarch64/tme.d: New test. * testsuite/gas/aarch64/tme.s: New test. *** include/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_TME): New. (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16. *** opcodes/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_IMM_NIL): New. (TME): New. (_TME_INSN): New. (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
396 lines
13 KiB
Plaintext
396 lines
13 KiB
Plaintext
2019-05-01 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* aarch64-asm-2.c: Regenerated.
|
||
* aarch64-dis-2.c: Regenerated.
|
||
* aarch64-opc-2.c: Regenerated.
|
||
* aarch64-opc.c (operand_general_constraint_met_p): Add case for
|
||
AARCH64_OPND_TME_UIMM16.
|
||
(aarch64_print_operand): Likewise.
|
||
* aarch64-tbl.h (QL_IMM_NIL): New.
|
||
(TME): New.
|
||
(_TME_INSN): New.
|
||
(struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
|
||
|
||
2019-04-29 John Darrington <john@darrington.wattle.id.au>
|
||
|
||
* s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
|
||
|
||
2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
|
||
Faraz Shahbazker <fshahbazker@wavecomp.com>
|
||
|
||
* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
|
||
|
||
2019-04-24 John Darrington <john@darrington.wattle.id.au>
|
||
|
||
* s12z-opc.h: Add extern "C" bracketing to help
|
||
users who wish to use this interface in c++ code.
|
||
|
||
2019-04-24 John Darrington <john@darrington.wattle.id.au>
|
||
|
||
* s12z-opc.c (bm_decode): Handle bit map operations with the
|
||
"reserved0" mode.
|
||
|
||
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
||
|
||
* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
|
||
specifier. Add entries for VLDR and VSTR of system registers.
|
||
(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
|
||
coprocessor instructions on Armv8.1-M Mainline targets. Add handling
|
||
of %J and %K format specifier.
|
||
|
||
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
||
|
||
* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
|
||
Add new entries for VSCCLRM instruction.
|
||
(print_insn_coprocessor): Handle new %C format control code.
|
||
|
||
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
||
|
||
* arm-dis.c (enum isa): New enum.
|
||
(struct sopcode32): New structure.
|
||
(coprocessor_opcodes): change type of entries to struct sopcode32 and
|
||
set isa field of all current entries to ANY.
|
||
(print_insn_coprocessor): Change type of insn to struct sopcode32.
|
||
Only match an entry if its isa field allows the current mode.
|
||
|
||
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
||
|
||
* arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
|
||
CLRM.
|
||
(print_insn_thumb32): Add logic to print %n CLRM register list.
|
||
|
||
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* arm-dis.c (print_insn_thumb32): Updated to accept new %P
|
||
and %Q patterns.
|
||
|
||
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
|
||
(print_insn_thumb32): Edit the switch case for %Z.
|
||
|
||
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
|
||
|
||
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* arm-dis.c (thumb32_opcodes): New instruction bfl.
|
||
|
||
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
|
||
|
||
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
|
||
Arm register with r13 and r15 unpredictable.
|
||
(thumb32_opcodes): New instructions for bfx and bflx.
|
||
|
||
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* arm-dis.c (thumb32_opcodes): New instructions for bf.
|
||
|
||
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
|
||
|
||
2019-04-15 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
|
||
|
||
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
||
|
||
* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
|
||
|
||
2019-04-12 John Darrington <john@darrington.wattle.id.au>
|
||
|
||
s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
|
||
"optr". ("operator" is a reserved word in c++).
|
||
|
||
2019-04-11 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_print_operand): Add case for
|
||
AARCH64_OPND_Rt_SP.
|
||
(verify_constraints): Likewise.
|
||
* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
|
||
(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
|
||
to accept Rt|SP as first operand.
|
||
(AARCH64_OPERANDS): Add new Rt_SP.
|
||
* aarch64-asm-2.c: Regenerated.
|
||
* aarch64-dis-2.c: Regenerated.
|
||
* aarch64-opc-2.c: Regenerated.
|
||
|
||
2019-04-11 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* aarch64-asm-2.c: Regenerated.
|
||
* aarch64-dis-2.c: Likewise.
|
||
* aarch64-opc-2.c: Likewise.
|
||
* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
|
||
|
||
2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
|
||
|
||
* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
|
||
|
||
2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-opc.tbl: Consolidate AVX512 BF16 entries.
|
||
* i386-init.h: Regenerated.
|
||
|
||
2019-04-07 Alan Modra <amodra@gmail.com>
|
||
|
||
* ppc-dis.c (print_insn_powerpc): Use a tiny state machine
|
||
op_separator to control printing of spaces, comma and parens
|
||
rather than need_comma, need_paren and spaces vars.
|
||
|
||
2019-04-07 Alan Modra <amodra@gmail.com>
|
||
|
||
PR 24421
|
||
* arm-dis.c (print_insn_coprocessor): Correct bracket placement.
|
||
(print_insn_neon, print_insn_arm): Likewise.
|
||
|
||
2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
|
||
|
||
* i386-dis-evex.h (evex_table): Updated to support BF16
|
||
instructions.
|
||
* i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
|
||
and EVEX_W_0F3872_P_3.
|
||
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
|
||
(cpu_flags): Add bitfield for CpuAVX512_BF16.
|
||
* i386-opc.h (enum): Add CpuAVX512_BF16.
|
||
(i386_cpu_flags): Add bitfield for cpuavx512_bf16.
|
||
* i386-opc.tbl: Add AVX512 BF16 instructions.
|
||
* i386-init.h: Regenerated.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2019-04-05 Alan Modra <amodra@gmail.com>
|
||
|
||
* ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
|
||
(powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
|
||
to favour printing of "-" branch hint when using the "y" bit.
|
||
Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
|
||
|
||
2019-04-05 Alan Modra <amodra@gmail.com>
|
||
|
||
* ppc-dis.c (print_insn_powerpc): Delay printing spaces after
|
||
opcode until first operand is output.
|
||
|
||
2019-04-04 Peter Bergner <bergner@linux.ibm.com>
|
||
|
||
PR gas/24349
|
||
* ppc-opc.c (valid_bo_pre_v2): Add comments.
|
||
(valid_bo_post_v2): Add support for 'at' branch hints.
|
||
(insert_bo): Only error on branch on ctr.
|
||
(get_bo_hint_mask): New function.
|
||
(insert_boe): Add new 'branch_taken' formal argument. Add support
|
||
for inserting 'at' branch hints.
|
||
(extract_boe): Add new 'branch_taken' formal argument. Add support
|
||
for extracting 'at' branch hints.
|
||
(insert_bom, extract_bom, insert_bop, extract_bop): New functions.
|
||
(BOE): Delete operand.
|
||
(BOM, BOP): New operands.
|
||
(RM): Update value.
|
||
(XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
|
||
(powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
|
||
bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
|
||
(powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
|
||
bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
|
||
<bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
|
||
bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
|
||
bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
|
||
bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
|
||
bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
|
||
bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
|
||
bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
|
||
bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
|
||
beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
|
||
bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
|
||
buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
|
||
bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
|
||
bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
|
||
bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
|
||
bttarl+>: New extended mnemonics.
|
||
|
||
2019-03-28 Alan Modra <amodra@gmail.com>
|
||
|
||
PR 24390
|
||
* ppc-opc.c (BTF): Define.
|
||
(powerpc_opcodes): Use for mtfsb*.
|
||
* ppc-dis.c (print_insn_powerpc): Print fields with both
|
||
PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
|
||
|
||
2019-03-25 Tamar Christina <tamar.christina@arm.com>
|
||
|
||
* arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
|
||
(mapping_symbol_for_insn): Implement new algorithm.
|
||
(print_insn): Remove duplicate code.
|
||
|
||
2019-03-25 Tamar Christina <tamar.christina@arm.com>
|
||
|
||
* aarch64-dis.c (print_insn_aarch64):
|
||
Implement override.
|
||
|
||
2019-03-25 Tamar Christina <tamar.christina@arm.com>
|
||
|
||
* aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
|
||
order.
|
||
|
||
2019-03-25 Tamar Christina <tamar.christina@arm.com>
|
||
|
||
* aarch64-dis.c (last_stop_offset): New.
|
||
(print_insn_aarch64): Use stop_offset.
|
||
|
||
2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
PR gas/24359
|
||
* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
|
||
CPU_ANY_AVX2_FLAGS.
|
||
* i386-init.h: Regenerated.
|
||
|
||
2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
PR gas/24348
|
||
* i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
|
||
vmovdqu16, vmovdqu32 and vmovdqu64.
|
||
* i386-tbl.h: Regenerated.
|
||
|
||
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
|
||
|
||
* s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
|
||
from vstrszb, vstrszh, and vstrszf.
|
||
|
||
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
|
||
|
||
* s390-opc.txt: Add instruction descriptions.
|
||
|
||
2019-02-08 Jim Wilson <jimw@sifive.com>
|
||
|
||
* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
|
||
<bne>: Likewise.
|
||
|
||
2019-02-07 Tamar Christina <tamar.christina@arm.com>
|
||
|
||
* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
|
||
|
||
2019-02-07 Tamar Christina <tamar.christina@arm.com>
|
||
|
||
PR binutils/23212
|
||
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
|
||
* aarch64-opc.c (verify_elem_sd): New.
|
||
(fields): Add FLD_sz entr.
|
||
* aarch64-tbl.h (_SIMD_INSN): New.
|
||
(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
|
||
fmulx scalar and vector by element isns.
|
||
|
||
2019-02-07 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/sv.po: Updated Swedish translation.
|
||
|
||
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
|
||
|
||
* s390-mkopc.c (main): Accept arch13 as cpu string.
|
||
* s390-opc.c: Add new instruction formats and instruction opcode
|
||
masks.
|
||
* s390-opc.txt: Add new arch13 instructions.
|
||
|
||
2019-01-25 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* aarch64-tbl.h (QL_LDST_AT): Update macro.
|
||
(aarch64_opcode): Change encoding for stg, stzg
|
||
st2g and st2zg.
|
||
* aarch64-asm-2.c: Regenerated.
|
||
* aarch64-dis-2.c: Regenerated.
|
||
* aarch64-opc-2.c: Regenerated.
|
||
|
||
2019-01-25 Sudakshina Das <sudi.das@arm.com>
|
||
|
||
* aarch64-asm-2.c: Regenerated.
|
||
* aarch64-dis-2.c: Likewise.
|
||
* aarch64-opc-2.c: Likewise.
|
||
* aarch64-tbl.h (aarch64_opcode): Add new stzgm.
|
||
|
||
2019-01-25 Sudakshina Das <sudi.das@arm.com>
|
||
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
|
||
|
||
* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
|
||
* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
|
||
* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
|
||
* aarch64-dis.h (ext_addr_simple_2): Likewise.
|
||
* aarch64-opc.c (operand_general_constraint_met_p): Remove
|
||
case for ldstgv_indexed.
|
||
(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
|
||
* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
|
||
(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
|
||
* aarch64-asm-2.c: Regenerated.
|
||
* aarch64-dis-2.c: Regenerated.
|
||
* aarch64-opc-2.c: Regenerated.
|
||
|
||
2019-01-23 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/pt_BR.po: Updated Brazilian Portuguese translation.
|
||
|
||
2019-01-21 Nick Clifton <nickc@redhat.com>
|
||
|
||
* po/de.po: Updated German translation.
|
||
* po/uk.po: Updated Ukranian translation.
|
||
|
||
2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
|
||
* mips-dis.c (mips_arch_choices): Fix typo in
|
||
gs464, gs464e and gs264e descriptors.
|
||
|
||
2019-01-19 Nick Clifton <nickc@redhat.com>
|
||
|
||
* configure: Regenerate.
|
||
* po/opcodes.pot: Regenerate.
|
||
|
||
2018-06-24 Nick Clifton <nickc@redhat.com>
|
||
|
||
2.32 branch created.
|
||
|
||
2019-01-09 John Darrington <john@darrington.wattle.id.au>
|
||
|
||
* s12z-dis.c (print_insn_s12z): Do not dereference an operand
|
||
if it is null.
|
||
-dis.c (opr_emit_disassembly): Do not omit an index if it is
|
||
zero.
|
||
|
||
2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
|
||
|
||
* configure: Regenerate.
|
||
|
||
2019-01-07 Alan Modra <amodra@gmail.com>
|
||
|
||
* configure: Regenerate.
|
||
* po/POTFILES.in: Regenerate.
|
||
|
||
2019-01-03 John Darrington <john@darrington.wattle.id.au>
|
||
|
||
* s12z-opc.c: New file.
|
||
* s12z-opc.h: New file.
|
||
* s12z-dis.c: Removed all code not directly related to display
|
||
of instructions. Used the interface provided by the new files
|
||
instead.
|
||
* Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
|
||
* Makefile.in: Regenerate.
|
||
* configure.ac (bfd_s12z_arch): Correct the dependencies.
|
||
* configure: Regenerate.
|
||
|
||
2019-01-01 Alan Modra <amodra@gmail.com>
|
||
|
||
Update year range in copyright notice of all files.
|
||
|
||
For older changes see ChangeLog-2018
|
||
|
||
Copyright (C) 2019 Free Software Foundation, Inc.
|
||
|
||
Copying and distribution of this file, with or without modification,
|
||
are permitted in any medium without royalty provided the copyright
|
||
notice and this notice are preserved.
|
||
|
||
Local Variables:
|
||
mode: change-log
|
||
left-margin: 8
|
||
fill-column: 74
|
||
version-control: never
|
||
End:
|