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1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
384 lines
7.3 KiB
C
384 lines
7.3 KiB
C
/* Support code for various pieces of CGEN simulators.
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Copyright (C) 1996-2024 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#include "bfd.h"
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#include "dis-asm.h"
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#include "sim-main.h"
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#include "sim-signal.h"
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#define MEMOPS_DEFINE_INLINE
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#include "cgen-mem.h"
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#define SEMOPS_DEFINE_INLINE
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#include "cgen-ops.h"
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const char * const cgen_mode_names[] = {
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"VOID",
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"BI",
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"QI",
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"HI",
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"SI",
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"DI",
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"UQI",
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"UHI",
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"USI",
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"UDI",
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"SF",
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"DF",
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"XF",
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"TF",
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0, /* MODE_TARGET_MAX */
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"INT",
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"UINT",
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"PTR"
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};
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/* Opcode table for virtual insns used by the simulator. */
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#define V CGEN_ATTR_MASK (CGEN_INSN_VIRTUAL)
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static const CGEN_IBASE virtual_insn_entries[] =
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{
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{
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VIRTUAL_INSN_X_INVALID, "--invalid--", NULL, 0, { V, {} }
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},
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{
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VIRTUAL_INSN_X_BEFORE, "--before--", NULL, 0, { V, {} }
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},
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{
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VIRTUAL_INSN_X_AFTER, "--after--", NULL, 0, { V, {} }
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},
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{
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VIRTUAL_INSN_X_BEGIN, "--begin--", NULL, 0, { V, {} }
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},
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{
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VIRTUAL_INSN_X_CHAIN, "--chain--", NULL, 0, { V, {} }
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},
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{
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VIRTUAL_INSN_X_CTI_CHAIN, "--cti-chain--", NULL, 0, { V, {} }
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}
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};
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#undef V
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const CGEN_INSN cgen_virtual_insn_table[] =
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{
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{ & virtual_insn_entries[0] },
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{ & virtual_insn_entries[1] },
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{ & virtual_insn_entries[2] },
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{ & virtual_insn_entries[3] },
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{ & virtual_insn_entries[4] },
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{ & virtual_insn_entries[5] }
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};
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/* Return the name of insn number I. */
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const char *
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cgen_insn_name (SIM_CPU *cpu, int i)
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{
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return CGEN_INSN_NAME ((* CPU_GET_IDATA (cpu)) ((cpu), (i)));
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}
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/* Return the maximum number of extra bytes required for a SIM_CPU struct. */
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int
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cgen_cpu_max_extra_bytes (SIM_DESC sd)
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{
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const SIM_MACH * const *machp;
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int extra = 0;
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SIM_ASSERT (STATE_MACHS (sd) != NULL);
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for (machp = STATE_MACHS (sd); *machp != NULL; ++machp)
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{
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int size = IMP_PROPS_SIM_CPU_SIZE (MACH_IMP_PROPS (*machp));
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if (size > extra)
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extra = size;
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}
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return extra;
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}
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#ifdef DI_FN_SUPPORT
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DI
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ANDDI (a, b)
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DI a, b;
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{
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SI ahi = GETHIDI (a);
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SI alo = GETLODI (a);
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SI bhi = GETHIDI (b);
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SI blo = GETLODI (b);
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return MAKEDI (ahi & bhi, alo & blo);
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}
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DI
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ORDI (a, b)
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DI a, b;
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{
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SI ahi = GETHIDI (a);
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SI alo = GETLODI (a);
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SI bhi = GETHIDI (b);
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SI blo = GETLODI (b);
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return MAKEDI (ahi | bhi, alo | blo);
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}
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DI
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ADDDI (a, b)
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DI a, b;
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{
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USI ahi = GETHIDI (a);
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USI alo = GETLODI (a);
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USI bhi = GETHIDI (b);
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USI blo = GETLODI (b);
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USI x = alo + blo;
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return MAKEDI (ahi + bhi + (x < alo), x);
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}
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DI
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MULDI (a, b)
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DI a, b;
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{
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USI ahi = GETHIDI (a);
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USI alo = GETLODI (a);
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USI bhi = GETHIDI (b);
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USI blo = GETLODI (b);
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USI rhi,rlo;
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USI x0, x1, x2, x3;
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x0 = alo * blo;
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x1 = alo * bhi;
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x2 = ahi * blo;
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x3 = ahi * bhi;
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#define SI_TYPE_SIZE 32
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#define BITS4 (SI_TYPE_SIZE / 4)
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#define ll_B (1L << (SI_TYPE_SIZE / 2))
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#define ll_lowpart(t) ((USI) (t) % ll_B)
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#define ll_highpart(t) ((USI) (t) / ll_B)
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x1 += ll_highpart (x0); /* this can't give carry */
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x1 += x2; /* but this indeed can */
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if (x1 < x2) /* did we get it? */
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x3 += ll_B; /* yes, add it in the proper pos. */
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rhi = x3 + ll_highpart (x1);
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rlo = ll_lowpart (x1) * ll_B + ll_lowpart (x0);
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return MAKEDI (rhi + (alo * bhi) + (ahi * blo), rlo);
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}
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DI
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SHLDI (val, shift)
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DI val;
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SI shift;
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{
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USI hi = GETHIDI (val);
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USI lo = GETLODI (val);
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/* FIXME: Need to worry about shift < 0 || shift >= 32. */
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return MAKEDI ((hi << shift) | (lo >> (32 - shift)), lo << shift);
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}
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DI
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SLADI (val, shift)
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DI val;
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SI shift;
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{
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SI hi = GETHIDI (val);
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USI lo = GETLODI (val);
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/* FIXME: Need to worry about shift < 0 || shift >= 32. */
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return MAKEDI ((hi << shift) | (lo >> (32 - shift)), lo << shift);
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}
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DI
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SRADI (val, shift)
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DI val;
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SI shift;
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{
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SI hi = GETHIDI (val);
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USI lo = GETLODI (val);
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/* We use SRASI because the result is implementation defined if hi < 0. */
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/* FIXME: Need to worry about shift < 0 || shift >= 32. */
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return MAKEDI (SRASI (hi, shift), (hi << (32 - shift)) | (lo >> shift));
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}
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int
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GEDI (a, b)
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DI a, b;
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{
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SI ahi = GETHIDI (a);
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USI alo = GETLODI (a);
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SI bhi = GETHIDI (b);
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USI blo = GETLODI (b);
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if (ahi > bhi)
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return 1;
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if (ahi == bhi)
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return alo >= blo;
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return 0;
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}
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int
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LEDI (a, b)
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DI a, b;
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{
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SI ahi = GETHIDI (a);
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USI alo = GETLODI (a);
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SI bhi = GETHIDI (b);
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USI blo = GETLODI (b);
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if (ahi < bhi)
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return 1;
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if (ahi == bhi)
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return alo <= blo;
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return 0;
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}
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DI
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CONVHIDI (val)
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HI val;
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{
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if (val < 0)
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return MAKEDI (-1, val);
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else
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return MAKEDI (0, val);
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}
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DI
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CONVSIDI (val)
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SI val;
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{
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if (val < 0)
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return MAKEDI (-1, val);
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else
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return MAKEDI (0, val);
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}
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SI
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CONVDISI (val)
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DI val;
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{
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return GETLODI (val);
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}
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#endif /* DI_FN_SUPPORT */
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QI
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RORQI (QI val, int shift)
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{
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if (shift != 0)
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{
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int remain = 8 - shift;
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int mask = (1 << shift) - 1;
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QI result = (val & mask) << remain;
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mask = (1 << remain) - 1;
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result |= (val >> shift) & mask;
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return result;
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}
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return val;
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}
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QI
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ROLQI (QI val, int shift)
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{
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if (shift != 0)
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{
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int remain = 8 - shift;
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int mask = (1 << remain) - 1;
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QI result = (val & mask) << shift;
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mask = (1 << shift) - 1;
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result |= (val >> remain) & mask;
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return result;
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}
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return val;
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}
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HI
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RORHI (HI val, int shift)
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{
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if (shift != 0)
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{
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int remain = 16 - shift;
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int mask = (1 << shift) - 1;
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HI result = (val & mask) << remain;
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mask = (1 << remain) - 1;
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result |= (val >> shift) & mask;
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return result;
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}
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return val;
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}
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HI
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ROLHI (HI val, int shift)
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{
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if (shift != 0)
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{
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int remain = 16 - shift;
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int mask = (1 << remain) - 1;
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HI result = (val & mask) << shift;
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mask = (1 << shift) - 1;
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result |= (val >> remain) & mask;
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return result;
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}
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return val;
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}
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SI
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RORSI (SI val, int shift)
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{
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if (shift != 0)
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{
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int remain = 32 - shift;
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int mask = (1 << shift) - 1;
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SI result = (val & mask) << remain;
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mask = (1 << remain) - 1;
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result |= (val >> shift) & mask;
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return result;
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}
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return val;
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}
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SI
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ROLSI (SI val, int shift)
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{
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if (shift != 0)
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{
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int remain = 32 - shift;
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int mask = (1 << remain) - 1;
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SI result = (val & mask) << shift;
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mask = (1 << shift) - 1;
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result |= (val >> remain) & mask;
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return result;
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}
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return val;
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}
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/* Emit an error message from CGEN RTL. */
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void
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cgen_rtx_error (SIM_CPU *cpu, const char * msg)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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sim_io_printf (sd, "%s", msg);
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sim_io_printf (sd, "\n");
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sim_engine_halt (sd, cpu, NULL, CPU_PC_GET (cpu), sim_stopped, SIM_SIGTRAP);
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}
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