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binutils-gdb/ld/testsuite/ld-riscv-elf
History
Nelson Chu aed44286ef RISC-V: Updated the default ISA spec to 20191213. 
Update the default ISA spec from 2.2 to 20191213 will change the default
version of i from 2.0 to 2.1.  Since zicsr and zifencei are separated
from i 2.1, users need to add them in the architecture string if they need
fence.i and csr instructions.  Besides, we also allow old ISA spec can
recognize zicsr and zifencei, but we won't output them since they are
already included in the i extension when i's version is less than 2.1.

bfd/
	* elfxx-riscv.c (riscv_parse_add_subset): Allow old ISA spec can
	recognize zicsr and zifencei.
gas/
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Updated to 20191213.
	* testsuite/gas/riscv/csr-version-1p10.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/option-arch-03.d: Updated i's version to 2.1.
	* testsuite/gas/riscv/option-arch-03.s: Likewise.
ld/
	* testsuite/ld-riscv-elf/call-relax.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated i's version to 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-01b.: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Added zifencei
	into Tag_RISCV_arch since it is added implied when i's version is
	larger than 2.1.
2022-01-07 18:48:29 +08:00
..
align-small-region.d RISC-V: Don't separate pcgp relaxation to another relax pass. 2021-10-22 16:44:37 +08:00
align-small-region.ld RISC-V: Don't separate pcgp relaxation to another relax pass. 2021-10-22 16:44:37 +08:00
align-small-region.s RISC-V: Don't separate pcgp relaxation to another relax pass. 2021-10-22 16:44:37 +08:00
attr-merge-arch-01.d RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-01a.s RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-01b.s RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-02.d RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-02a.s RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-02b.s RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-03.d RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-03a.s RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-03b.s RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-failed-01.d
attr-merge-arch-failed-01a.s
attr-merge-arch-failed-01b.s
attr-merge-arch-failed-02.d RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-failed-02a.s
attr-merge-arch-failed-02b.s
attr-merge-arch-failed-02c.s
attr-merge-arch-failed-02d.s
attr-merge-priv-spec-01.d
attr-merge-priv-spec-02.d
attr-merge-priv-spec-03.d
attr-merge-priv-spec-a.s
attr-merge-priv-spec-b.s
attr-merge-priv-spec-c.s
attr-merge-priv-spec-d.s
attr-merge-priv-spec-failed-01.d
attr-merge-priv-spec-failed-02.d
attr-merge-priv-spec-failed-03.d
attr-merge-priv-spec-failed-04.d
attr-merge-priv-spec-failed-05.d
attr-merge-priv-spec-failed-06.d
attr-merge-stack-align-a.s
attr-merge-stack-align-b.s
attr-merge-stack-align-failed-a.s
attr-merge-stack-align-failed-b.s
attr-merge-stack-align-failed.d
attr-merge-stack-align.d
attr-merge-strict-align-01.d
attr-merge-strict-align-01a.s
attr-merge-strict-align-01b.s
attr-merge-strict-align-02.d
attr-merge-strict-align-02a.s
attr-merge-strict-align-02b.s
attr-merge-strict-align-03.d
attr-merge-strict-align-03a.s
attr-merge-strict-align-03b.s
attr-merge-strict-align-04.d
attr-merge-strict-align-04a.s
attr-merge-strict-align-04b.s
attr-merge-strict-align-05.d
attr-merge-strict-align-05a.s
attr-merge-strict-align-05b.s
attr-phdr.d RISC-V: Add PT_RISCV_ATTRIBUTES and add it to PHDR. 2021-07-06 11:34:36 +08:00
attr-phdr.s RISC-V: Add PT_RISCV_ATTRIBUTES and add it to PHDR. 2021-07-06 11:34:36 +08:00
c-lui-2.d
c-lui-2.ld
c-lui-2.s
c-lui.d
c-lui.s
call-relax-0.s
call-relax-1.s
call-relax-2.s
call-relax-3.s
call-relax.d RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
code-model-01.ld RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-02.ld RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medany-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medany-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medany-weakref-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medany-weakref-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medlow-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medlow-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medlow-weakref-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medlow-weakref-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medany-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medany-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medany-weakref-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medany-weakref-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medlow-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medlow-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medlow-weakref-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medlow-weakref-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model.s RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
disas-jalr.d
disas-jalr.s
gp-test-lib.sd
gp-test.s
gp-test.sd
ifunc-nonplt-exe.rd
ifunc-nonplt-pic.rd
ifunc-nonplt-pie.rd
ifunc-nonplt.d
ifunc-nonplt.s
ifunc-plt-01-exe.rd
ifunc-plt-01-pic.rd
ifunc-plt-01-pie.rd
ifunc-plt-01.d
ifunc-plt-01.s
ifunc-plt-02-exe.rd
ifunc-plt-02-pic.rd
ifunc-plt-02-pie.rd
ifunc-plt-02.d
ifunc-plt-02.s
ifunc-plt-got-overwrite-exe.rd
ifunc-plt-got-overwrite-pic.rd
ifunc-plt-got-overwrite-pie.rd
ifunc-plt-got-overwrite.d
ifunc-plt-got-overwrite.s
ifunc-reloc-call-01-exe.rd
ifunc-reloc-call-01-pic.rd
ifunc-reloc-call-01-pie.rd
ifunc-reloc-call-01.d
ifunc-reloc-call-01.s
ifunc-reloc-call-02-exe.rd
ifunc-reloc-call-02-pic.rd
ifunc-reloc-call-02-pie.rd
ifunc-reloc-call-02.d
ifunc-reloc-call-02.s
ifunc-reloc-data-exe.rd
ifunc-reloc-data-pic.rd
ifunc-reloc-data-pie.rd
ifunc-reloc-data.d
ifunc-reloc-data.s
ifunc-reloc-got-exe.rd
ifunc-reloc-got-pic.rd
ifunc-reloc-got-pie.rd
ifunc-reloc-got.d
ifunc-reloc-got.s
ifunc-reloc-pcrel-exe.rd
ifunc-reloc-pcrel-pic.rd
ifunc-reloc-pcrel-pie.rd
ifunc-reloc-pcrel.d
ifunc-reloc-pcrel.s
ifunc-seperate-caller-nonplt.s
ifunc-seperate-caller-pcrel.s
ifunc-seperate-caller-plt.s
ifunc-seperate-nonplt-exe.d
ifunc-seperate-nonplt-pic.d
ifunc-seperate-nonplt-pie.d
ifunc-seperate-pcrel-pic.d
ifunc-seperate-pcrel-pie.d
ifunc-seperate-plt-exe.d
ifunc-seperate-plt-pic.d
ifunc-seperate-plt-pie.d
ifunc-seperate-resolver.s
ld-riscv-elf.exp Update year range in copyright notice of binutils files 2022-01-02 12:04:28 +10:30
lib-nopic-01a.s
lib-nopic-01b.d
lib-nopic-01b.s
pcgp-relax-01.d RISC-V: Added ld testcase for pcgp relaxation. 2021-10-22 16:44:43 +08:00
pcgp-relax-01.s RISC-V: Added ld testcase for pcgp relaxation. 2021-10-22 16:44:43 +08:00
pcgp-relax-02.d RISC-V: Added ld testcase for pcgp relaxation. 2021-10-22 16:44:43 +08:00
pcgp-relax-02.s RISC-V: Added ld testcase for pcgp relaxation. 2021-10-22 16:44:43 +08:00
pcrel-lo-addend-2a.d
pcrel-lo-addend-2a.s
pcrel-lo-addend-2b.d
pcrel-lo-addend-2b.s
pcrel-lo-addend-3.ld RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend-3a.d RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend-3a.s RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend-3b.d RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend-3b.s RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend-3c.d RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend-3c.s RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend.d
pcrel-lo-addend.s
relax-twice-1.s elf/riscv: Fix relaxation with aliases [PR28021] 2021-07-06 15:49:03 +02:00
relax-twice-2.s elf/riscv: Fix relaxation with aliases [PR28021] 2021-07-06 15:49:03 +02:00
relax-twice.ver elf/riscv: Fix relaxation with aliases [PR28021] 2021-07-06 15:49:03 +02:00
relro-relax-lui.d
relro-relax-lui.s
relro-relax-pcrel.d
relro-relax-pcrel.s
variant_cc-1.s RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC. 2021-11-19 09:32:19 +08:00
variant_cc-2.s RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC. 2021-11-19 09:32:19 +08:00
variant_cc-now.d RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC. 2021-11-19 09:32:19 +08:00
variant_cc-r.d RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC. 2021-11-19 09:32:19 +08:00
variant_cc-shared.d RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC. 2021-11-19 09:32:19 +08:00
weakref32.d
weakref32.s
weakref64.d
weakref64.s
weakref.ld