mirror of
https://sourceware.org/git/binutils-gdb.git
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3d5a60de52
For mov name@GOTPCREL(%rip), %reg test %reg, name@GOTPCREL(%rip) binop name@GOTPCREL(%rip), %reg where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions, add # define R_X86_64_CODE_4_GOTPCRELX 43 if the instruction starts at 4 bytes before the relocation offset. It similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX as R_X86_64_GOTPCREL or convert the above instructions to lea name(%rip), %reg mov $name, %reg test $name, %reg binop $name, %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTPCRELX. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_convert_load_reloc): Handle R_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * write.h (fix): Add fx_tcbit3. Change fx_unused to 1 bit. * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (tc_gen_reloc): Likewise. (output_disp): Set fixP->fx_tcbit3 for REX2 prefix. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTPCRELX if fixp->fx_tcbit3 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (TC_FORCE_RELOCATION_ABS): Likewise. * testsuite/gas/i386/x86-64-gotpcrel.s: Add tests for R_X86_64_CODE_4_GOTPCRELX. * testsuite/gas/i386/x86-64-localpic.s: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Updated. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTPCRELX. ld/ * testsuite/ld-x86-64/apx-load1.s: New file. * testsuite/ld-x86-64/apx-load1a.d: Likewise. * testsuite/ld-x86-64/apx-load1b.d: Likewise. * testsuite/ld-x86-64/apx-load1c.d: Likewise. * testsuite/ld-x86-64/apx-load1d.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run apx-load1a, apx-load1b, apx-load1c and apx-load1d.
48 lines
3.3 KiB
Makefile
48 lines
3.3 KiB
Makefile
#source: apx-load1.s
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#as: --x32
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#ld: -shared -melf32_x86_64 --hash-style=sysv -z max-page-size=0x200000 -z noseparate-code $NO_DT_RELR_LDFLAGS
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#objdump: -dw
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.*: +file format .*
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Disassembly of section .text:
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0+100 <_start>:
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+[a-f0-9]+: d5 40 13 05 88 01 20 00 adc 0x200188\(%rip\),%r16d # 200290 <.*>
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+[a-f0-9]+: d5 40 03 0d 80 01 20 00 add 0x200180\(%rip\),%r17d # 200290 <.*>
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+[a-f0-9]+: d5 40 23 15 78 01 20 00 and 0x200178\(%rip\),%r18d # 200290 <.*>
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+[a-f0-9]+: d5 40 3b 1d 70 01 20 00 cmp 0x200170\(%rip\),%r19d # 200290 <.*>
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+[a-f0-9]+: d5 40 0b 25 68 01 20 00 or 0x200168\(%rip\),%r20d # 200290 <.*>
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+[a-f0-9]+: d5 40 1b 2d 60 01 20 00 sbb 0x200160\(%rip\),%r21d # 200290 <.*>
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+[a-f0-9]+: d5 40 2b 35 58 01 20 00 sub 0x200158\(%rip\),%r22d # 200290 <.*>
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+[a-f0-9]+: d5 40 33 3d 50 01 20 00 xor 0x200150\(%rip\),%r23d # 200290 <.*>
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+[a-f0-9]+: d5 44 85 05 48 01 20 00 test %r24d,0x200148\(%rip\) # 200290 <.*>
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+[a-f0-9]+: d5 48 13 05 40 01 20 00 adc 0x200140\(%rip\),%r16 # 200290 <.*>
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+[a-f0-9]+: d5 48 03 0d 38 01 20 00 add 0x200138\(%rip\),%r17 # 200290 <.*>
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+[a-f0-9]+: d5 48 23 15 30 01 20 00 and 0x200130\(%rip\),%r18 # 200290 <.*>
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+[a-f0-9]+: d5 48 3b 1d 28 01 20 00 cmp 0x200128\(%rip\),%r19 # 200290 <.*>
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+[a-f0-9]+: d5 48 0b 25 20 01 20 00 or 0x200120\(%rip\),%r20 # 200290 <.*>
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+[a-f0-9]+: d5 48 1b 2d 18 01 20 00 sbb 0x200118\(%rip\),%r21 # 200290 <.*>
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+[a-f0-9]+: d5 48 2b 35 10 01 20 00 sub 0x200110\(%rip\),%r22 # 200290 <.*>
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+[a-f0-9]+: d5 48 33 3d 08 01 20 00 xor 0x200108\(%rip\),%r23 # 200290 <.*>
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+[a-f0-9]+: d5 4c 85 05 00 01 20 00 test %r24,0x200100\(%rip\) # 200290 <.*>
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+[a-f0-9]+: d5 40 13 05 00 01 20 00 adc 0x200100\(%rip\),%r16d # 200298 <.*>
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+[a-f0-9]+: d5 40 03 0d f8 00 20 00 add 0x2000f8\(%rip\),%r17d # 200298 <.*>
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+[a-f0-9]+: d5 40 23 15 f0 00 20 00 and 0x2000f0\(%rip\),%r18d # 200298 <.*>
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+[a-f0-9]+: d5 40 3b 1d e8 00 20 00 cmp 0x2000e8\(%rip\),%r19d # 200298 <.*>
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+[a-f0-9]+: d5 40 0b 25 e0 00 20 00 or 0x2000e0\(%rip\),%r20d # 200298 <.*>
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+[a-f0-9]+: d5 40 1b 2d d8 00 20 00 sbb 0x2000d8\(%rip\),%r21d # 200298 <.*>
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+[a-f0-9]+: d5 40 2b 35 d0 00 20 00 sub 0x2000d0\(%rip\),%r22d # 200298 <.*>
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+[a-f0-9]+: d5 40 33 3d c8 00 20 00 xor 0x2000c8\(%rip\),%r23d # 200298 <.*>
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+[a-f0-9]+: d5 44 85 05 c0 00 20 00 test %r24d,0x2000c0\(%rip\) # 200298 <.*>
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+[a-f0-9]+: d5 48 13 05 b8 00 20 00 adc 0x2000b8\(%rip\),%r16 # 200298 <.*>
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+[a-f0-9]+: d5 48 03 0d b0 00 20 00 add 0x2000b0\(%rip\),%r17 # 200298 <.*>
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+[a-f0-9]+: d5 48 23 15 a8 00 20 00 and 0x2000a8\(%rip\),%r18 # 200298 <.*>
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+[a-f0-9]+: d5 48 3b 1d a0 00 20 00 cmp 0x2000a0\(%rip\),%r19 # 200298 <.*>
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+[a-f0-9]+: d5 48 0b 25 98 00 20 00 or 0x200098\(%rip\),%r20 # 200298 <.*>
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+[a-f0-9]+: d5 48 1b 2d 90 00 20 00 sbb 0x200090\(%rip\),%r21 # 200298 <.*>
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+[a-f0-9]+: d5 48 2b 35 88 00 20 00 sub 0x200088\(%rip\),%r22 # 200298 <.*>
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+[a-f0-9]+: d5 48 33 3d 80 00 20 00 xor 0x200080\(%rip\),%r23 # 200298 <.*>
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+[a-f0-9]+: d5 4c 85 05 78 00 20 00 test %r24,0x200078\(%rip\) # 200298 <.*>
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#pass
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