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284a130902
The current PLT generation code will generate invalid code when the PLT relocation offset exceeds 64k. This fixes the issue by detecting large plt_reloc offsets and generare code sequences to create larger plt relocations. The "large" plt code needs 2 extra instructions to create 32-bit offsets. bfd/ChangeLog: PR 27746 * elf32-or1k.c (PLT_ENTRY_SIZE_LARGE, PLT_MAX_INSN_COUNT, OR1K_ADD, OR1K_ORI): New macros to help with plt creation. (elf_or1k_link_hash_table): New field plt_count. (elf_or1k_link_hash_entry): New field plt_index. (elf_or1k_plt_entry_size): New function. (or1k_write_plt_entry): Update to support variable size PLTs. (or1k_elf_finish_dynamic_sections): Use new or1k_write_plt_entry API. (or1k_elf_finish_dynamic_symbol): Update to write large PLTs when needed. (allocate_dynrelocs): Use elf_or1k_plt_entry_size to account for PLT size. ld/ChangeLog: PR 27746 testsuite/ld-or1k/or1k.exp (or1kplttests): Add tests for linking along with gotha() relocations. testsuite/ld-or1k/gotha1.dd: New file. testsuite/ld-or1k/gotha1.s: New file. testsuite/ld-or1k/gotha2.dd: New file. testsuite/ld-or1k/gotha2.s: New file testsuite/ld-or1k/pltlib.s (x): Define size to avoid link failure.
22 lines
742 B
Plaintext
22 lines
742 B
Plaintext
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.*\.x: file format elf32-or1k
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Disassembly of section \.text:
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[0-9a-f]+ <test>:
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+[0-9a-f]+: 9c 21 ff f8 l\.addi r1,r1,-8
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+[0-9a-f]+: d4 01 80 00 l\.sw 0\(r1\),r16
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+[0-9a-f]+: d4 01 48 04 l\.sw 4\(r1\),r9
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+[0-9a-f]+: 04 00 [0-9a-f]+ [0-9a-f]+ l\.jal [0-9a-f]+ <test\+0x14>
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+[0-9a-f]+: 1a 00 00 00 l\.movhi r16,0x0
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+[0-9a-f]+: aa 10 [0-9a-f]+ [0-9a-f]+ l\.ori r16,r16,0x[0-9a-f]+
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+[0-9a-f]+: e2 10 48 00 l\.add r16,r16,r9
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+[0-9a-f]+: 1a 20 00 00 l\.movhi r17,0x0
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+[0-9a-f]+: e2 31 80 00 l\.add r17,r17,r16
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+[0-9a-f]+: 86 31 00 0c l\.lwz r17,12\(r17\)
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+[0-9a-f]+: 85 21 00 04 l\.lwz r9,4\(r1\)
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+[0-9a-f]+: 86 01 00 00 l\.lwz r16,0\(r1\)
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+[0-9a-f]+: 44 00 48 00 l\.jr r9
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+[0-9a-f]+: 9c 21 00 08 l\.addi r1,r1,8
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