mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-27 04:52:05 +08:00
4aeddc50d7
Remove all macros related to getting and setting some symbol value:
#define SYMBOL_VALUE(symbol) (symbol)->value.ivalue
#define SYMBOL_VALUE_ADDRESS(symbol) \
#define SET_SYMBOL_VALUE_ADDRESS(symbol, new_value) \
#define SYMBOL_VALUE_BYTES(symbol) (symbol)->value.bytes
#define SYMBOL_VALUE_COMMON_BLOCK(symbol) (symbol)->value.common_block
#define SYMBOL_BLOCK_VALUE(symbol) (symbol)->value.block
#define SYMBOL_VALUE_CHAIN(symbol) (symbol)->value.chain
#define MSYMBOL_VALUE(symbol) (symbol)->value.ivalue
#define MSYMBOL_VALUE_RAW_ADDRESS(symbol) ((symbol)->value.address + 0)
#define MSYMBOL_VALUE_ADDRESS(objfile, symbol) \
#define BMSYMBOL_VALUE_ADDRESS(symbol) \
#define SET_MSYMBOL_VALUE_ADDRESS(symbol, new_value) \
#define MSYMBOL_VALUE_BYTES(symbol) (symbol)->value.bytes
#define MSYMBOL_BLOCK_VALUE(symbol) (symbol)->value.block
Replace them with equivalent methods on the appropriate objects.
Change-Id: Iafdab3b8eefc6dc2fd895aa955bf64fafc59ed50
1466 lines
45 KiB
C
1466 lines
45 KiB
C
/* Target-dependent code for the Z80.
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Copyright (C) 1986-2022 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "arch-utils.h"
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#include "dis-asm.h"
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#include "frame.h"
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#include "frame-unwind.h"
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#include "frame-base.h"
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#include "trad-frame.h"
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#include "gdbcmd.h"
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#include "gdbcore.h"
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#include "gdbtypes.h"
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#include "inferior.h"
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#include "objfiles.h"
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#include "symfile.h"
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#include "gdbarch.h"
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#include "z80-tdep.h"
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#include "features/z80.c"
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/* You need to define __gdb_break_handler symbol pointing to the breakpoint
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handler. The value of the symbol will be used to determine the instruction
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for software breakpoint. If __gdb_break_handler points to one of standard
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RST addresses (0x00, 0x08, 0x10,... 0x38) then RST __gdb_break_handler
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instruction will be used, else CALL __gdb_break_handler
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;breakpoint handler
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.globl __gdb_break_handler
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.org 8
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__gdb_break_handler:
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jp _debug_swbreak
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*/
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/* Meaning of terms "previous" and "next":
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previous frame - frame of callee, which is called by current function
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current frame - frame of current function which has called callee
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next frame - frame of caller, which has called current function
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*/
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struct z80_gdbarch_tdep : gdbarch_tdep
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{
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/* Number of bytes used for address:
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2 bytes for all Z80 family
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3 bytes for eZ80 CPUs operating in ADL mode */
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int addr_length = 0;
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/* Type for void. */
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struct type *void_type = nullptr;
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/* Type for a function returning void. */
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struct type *func_void_type = nullptr;
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/* Type for a pointer to a function. Used for the type of PC. */
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struct type *pc_type = nullptr;
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};
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/* At any time stack frame contains following parts:
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[<current PC>]
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[<temporaries, y bytes>]
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[<local variables, x bytes>
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<next frame FP>]
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[<saved state (critical or interrupt functions), 2 or 10 bytes>]
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In simplest case <next PC> is pointer to the call instruction
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(or call __call_hl). There are more difficult cases: interrupt handler or
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push/ret and jp; but they are untrackable.
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*/
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struct z80_unwind_cache
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{
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/* The previous frame's inner most stack address (SP after call executed),
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it is current frame's frame_id. */
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CORE_ADDR prev_sp;
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/* Size of the frame, prev_sp + size = next_frame.prev_sp */
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ULONGEST size;
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/* size of saved state (including frame pointer and return address),
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assume: prev_sp + size = IX + state_size */
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ULONGEST state_size;
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struct
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{
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int called:1; /* there is return address on stack */
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int load_args:1; /* prologues loads args using POPs */
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int fp_sdcc:1; /* prologue saves and adjusts frame pointer IX */
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int interrupt:1; /* __interrupt handler */
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int critical:1; /* __critical function */
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} prologue_type;
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/* Table indicating the location of each and every register. */
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struct trad_frame_saved_reg *saved_regs;
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};
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enum instruction_type
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{
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insn_default,
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insn_z80,
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insn_adl,
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insn_z80_ed,
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insn_adl_ed,
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insn_z80_ddfd,
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insn_adl_ddfd,
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insn_djnz_d,
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insn_jr_d,
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insn_jr_cc_d,
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insn_jp_nn,
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insn_jp_rr,
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insn_jp_cc_nn,
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insn_call_nn,
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insn_call_cc_nn,
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insn_rst_n,
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insn_ret,
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insn_ret_cc,
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insn_push_rr,
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insn_pop_rr,
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insn_dec_sp,
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insn_inc_sp,
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insn_ld_sp_nn,
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insn_ld_sp_6nn9, /* ld sp, (nn) */
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insn_ld_sp_rr,
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insn_force_nop /* invalid opcode prefix */
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};
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struct insn_info
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{
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gdb_byte code;
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gdb_byte mask;
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gdb_byte size; /* without prefix(es) */
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enum instruction_type type;
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};
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/* Constants */
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static const struct insn_info *
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z80_get_insn_info (struct gdbarch *gdbarch, const gdb_byte *buf, int *size);
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static const char *z80_reg_names[] =
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{
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/* 24 bit on eZ80, else 16 bit */
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"af", "bc", "de", "hl",
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"sp", "pc", "ix", "iy",
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"af'", "bc'", "de'", "hl'",
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"ir",
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/* eZ80 only */
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"sps"
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};
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/* Return the name of register REGNUM. */
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static const char *
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z80_register_name (struct gdbarch *gdbarch, int regnum)
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{
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if (regnum >= 0 && regnum < ARRAY_SIZE (z80_reg_names))
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return z80_reg_names[regnum];
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return NULL;
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}
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/* Return the type of a register specified by the architecture. Only
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the register cache should call this function directly; others should
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use "register_type". */
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static struct type *
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z80_register_type (struct gdbarch *gdbarch, int reg_nr)
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{
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return builtin_type (gdbarch)->builtin_data_ptr;
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}
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/* The next 2 functions check BUF for instruction. If it is pop/push rr, then
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it returns register number OR'ed with 0x100 */
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static int
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z80_is_pop_rr (const gdb_byte buf[], int *size)
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{
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switch (buf[0])
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{
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case 0xc1:
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*size = 1;
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return Z80_BC_REGNUM | 0x100;
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case 0xd1:
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*size = 1;
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return Z80_DE_REGNUM | 0x100;
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case 0xe1:
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*size = 1;
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return Z80_HL_REGNUM | 0x100;
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case 0xf1:
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*size = 1;
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return Z80_AF_REGNUM | 0x100;
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case 0xdd:
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*size = 2;
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return (buf[1] == 0xe1) ? (Z80_IX_REGNUM | 0x100) : 0;
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case 0xfd:
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*size = 2;
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return (buf[1] == 0xe1) ? (Z80_IY_REGNUM | 0x100) : 0;
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}
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*size = 0;
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return 0;
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}
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static int
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z80_is_push_rr (const gdb_byte buf[], int *size)
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{
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switch (buf[0])
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{
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case 0xc5:
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*size = 1;
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return Z80_BC_REGNUM | 0x100;
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case 0xd5:
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*size = 1;
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return Z80_DE_REGNUM | 0x100;
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case 0xe5:
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*size = 1;
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return Z80_HL_REGNUM | 0x100;
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case 0xf5:
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*size = 1;
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return Z80_AF_REGNUM | 0x100;
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case 0xdd:
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*size = 2;
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return (buf[1] == 0xe5) ? (Z80_IX_REGNUM | 0x100) : 0;
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case 0xfd:
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*size = 2;
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return (buf[1] == 0xe5) ? (Z80_IY_REGNUM | 0x100) : 0;
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}
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*size = 0;
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return 0;
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}
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/* Function: z80_scan_prologue
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This function decodes a function prologue to determine:
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1) the size of the stack frame
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2) which registers are saved on it
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3) the offsets of saved regs
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This information is stored in the z80_unwind_cache structure.
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Small SDCC functions may just load args using POP instructions in prologue:
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pop af
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pop de
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pop hl
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pop bc
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push bc
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push hl
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push de
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push af
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SDCC function prologue may have up to 3 sections (all are optional):
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1) save state
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a) __critical functions:
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ld a,i
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di
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push af
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b) __interrupt (both int and nmi) functions:
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push af
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push bc
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push de
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push hl
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push iy
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2) save and adjust frame pointer
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a) call to special function (size optimization)
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call ___sdcc_enter_ix
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b) inline (speed optimization)
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push ix
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ld ix, #0
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add ix, sp
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c) without FP, but saving it (IX is optimized out)
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push ix
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3) allocate local variables
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a) via series of PUSH AF and optional DEC SP (size optimization)
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push af
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...
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push af
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dec sp ;optional, if allocated odd numbers of bytes
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b) via SP decrements
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dec sp
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...
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dec sp
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c) via addition (for large frames: 5+ for speed and 9+ for size opt.)
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ld hl, #xxxx ;size of stack frame
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add hl, sp
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ld sp, hl
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d) same, but using register IY (arrays or for __z88dk_fastcall functions)
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ld iy, #xxxx ;size of stack frame
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add iy, sp
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ld sp, iy
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e) same as c, but for eZ80
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lea hl, ix - #nn
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ld sp, hl
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f) same as d, but for eZ80
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lea iy, ix - #nn
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ld sp, iy
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*/
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static int
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z80_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR pc_beg, CORE_ADDR pc_end,
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struct z80_unwind_cache *info)
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{
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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z80_gdbarch_tdep *tdep = (z80_gdbarch_tdep *) gdbarch_tdep (gdbarch);
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int addr_len = tdep->addr_length;
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gdb_byte prologue[32]; /* max prologue is 24 bytes: __interrupt with local array */
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int pos = 0;
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int len;
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int reg;
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CORE_ADDR value;
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len = pc_end - pc_beg;
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if (len > (int)sizeof (prologue))
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len = sizeof (prologue);
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read_memory (pc_beg, prologue, len);
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/* stage0: check for series of POPs and then PUSHs */
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if ((reg = z80_is_pop_rr(prologue, &pos)))
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{
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int i;
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int size = pos;
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gdb_byte regs[8]; /* Z80 have only 6 register pairs */
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regs[0] = reg & 0xff;
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for (i = 1; i < 8 && (regs[i] = z80_is_pop_rr (&prologue[pos], &size));
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++i, pos += size);
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/* now we expect series of PUSHs in reverse order */
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for (--i; i >= 0 && regs[i] == z80_is_push_rr (&prologue[pos], &size);
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--i, pos += size);
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if (i == -1 && pos > 0)
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info->prologue_type.load_args = 1;
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else
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pos = 0;
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}
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/* stage1: check for __interrupt handlers and __critical functions */
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else if (!memcmp (&prologue[pos], "\355\127\363\365", 4))
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{ /* ld a, i; di; push af */
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info->prologue_type.critical = 1;
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pos += 4;
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info->state_size += addr_len;
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}
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else if (!memcmp (&prologue[pos], "\365\305\325\345\375\345", 6))
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{ /* push af; push bc; push de; push hl; push iy */
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info->prologue_type.interrupt = 1;
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pos += 6;
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info->state_size += addr_len * 5;
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}
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/* stage2: check for FP saving scheme */
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if (prologue[pos] == 0xcd) /* call nn */
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{
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struct bound_minimal_symbol msymbol;
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msymbol = lookup_minimal_symbol ("__sdcc_enter_ix", NULL, NULL);
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if (msymbol.minsym)
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{
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value = msymbol.value_address ();
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if (value == extract_unsigned_integer (&prologue[pos+1], addr_len, byte_order))
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{
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pos += 1 + addr_len;
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info->prologue_type.fp_sdcc = 1;
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}
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}
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}
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else if (!memcmp (&prologue[pos], "\335\345\335\041\000\000", 4+addr_len) &&
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!memcmp (&prologue[pos+4+addr_len], "\335\071\335\371", 4))
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{ /* push ix; ld ix, #0; add ix, sp; ld sp, ix */
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pos += 4 + addr_len + 4;
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info->prologue_type.fp_sdcc = 1;
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}
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else if (!memcmp (&prologue[pos], "\335\345", 2))
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{ /* push ix */
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pos += 2;
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info->prologue_type.fp_sdcc = 1;
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}
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/* stage3: check for local variables allocation */
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switch (prologue[pos])
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{
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case 0xf5: /* push af */
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info->size = 0;
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while (prologue[pos] == 0xf5)
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{
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info->size += addr_len;
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pos++;
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}
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if (prologue[pos] == 0x3b) /* dec sp */
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{
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info->size++;
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pos++;
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}
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break;
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case 0x3b: /* dec sp */
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info->size = 0;
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while (prologue[pos] == 0x3b)
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{
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info->size++;
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pos++;
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}
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break;
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case 0x21: /*ld hl, -nn */
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if (prologue[pos+addr_len] == 0x39 && prologue[pos+addr_len] >= 0x80 &&
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prologue[pos+addr_len+1] == 0xf9)
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{ /* add hl, sp; ld sp, hl */
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info->size = -extract_signed_integer(&prologue[pos+1], addr_len, byte_order);
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pos += 1 + addr_len + 2;
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}
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break;
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case 0xfd: /* ld iy, -nn */
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if (prologue[pos+1] == 0x21 && prologue[pos+1+addr_len] >= 0x80 &&
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!memcmp (&prologue[pos+2+addr_len], "\375\071\375\371", 4))
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{
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info->size = -extract_signed_integer(&prologue[pos+2], addr_len, byte_order);
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pos += 2 + addr_len + 4;
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}
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break;
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case 0xed: /* check for lea xx, ix - n */
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switch (prologue[pos+1])
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{
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case 0x22: /* lea hl, ix - n */
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if (prologue[pos+2] >= 0x80 && prologue[pos+3] == 0xf9)
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{ /* ld sp, hl */
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info->size = -extract_signed_integer(&prologue[pos+2], 1, byte_order);
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pos += 4;
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}
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break;
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case 0x55: /* lea iy, ix - n */
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if (prologue[pos+2] >= 0x80 && prologue[pos+3] == 0xfd &&
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prologue[pos+4] == 0xf9)
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{ /* ld sp, iy */
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info->size = -extract_signed_integer(&prologue[pos+2], 1, byte_order);
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pos += 5;
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}
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break;
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}
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break;
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}
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len = 0;
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if (info->prologue_type.interrupt)
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{
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info->saved_regs[Z80_AF_REGNUM].set_addr (len++);
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info->saved_regs[Z80_BC_REGNUM].set_addr (len++);
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info->saved_regs[Z80_DE_REGNUM].set_addr (len++);
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info->saved_regs[Z80_HL_REGNUM].set_addr (len++);
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info->saved_regs[Z80_IY_REGNUM].set_addr (len++);
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}
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if (info->prologue_type.critical)
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len++; /* just skip IFF2 saved state */
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if (info->prologue_type.fp_sdcc)
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info->saved_regs[Z80_IX_REGNUM].set_addr (len++);
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info->state_size += len * addr_len;
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return pc_beg + pos;
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}
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static CORE_ADDR
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z80_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
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{
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CORE_ADDR func_addr, func_end;
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CORE_ADDR prologue_end;
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if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
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return pc;
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prologue_end = skip_prologue_using_sal (gdbarch, func_addr);
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if (prologue_end != 0)
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return std::max (pc, prologue_end);
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{
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struct z80_unwind_cache info = {0};
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struct trad_frame_saved_reg saved_regs[Z80_NUM_REGS];
|
|
|
|
info.saved_regs = saved_regs;
|
|
|
|
/* Need to run the prologue scanner to figure out if the function has a
|
|
prologue. */
|
|
|
|
prologue_end = z80_scan_prologue (gdbarch, func_addr, func_end, &info);
|
|
|
|
if (info.prologue_type.fp_sdcc || info.prologue_type.interrupt ||
|
|
info.prologue_type.critical)
|
|
return std::max (pc, prologue_end);
|
|
}
|
|
|
|
if (prologue_end != 0)
|
|
{
|
|
struct symtab_and_line prologue_sal = find_pc_line (func_addr, 0);
|
|
struct compunit_symtab *compunit = prologue_sal.symtab->compunit ();
|
|
const char *debug_format = compunit->debugformat ();
|
|
|
|
if (debug_format != NULL &&
|
|
!strncasecmp ("dwarf", debug_format, strlen("dwarf")))
|
|
return std::max (pc, prologue_end);
|
|
}
|
|
|
|
return pc;
|
|
}
|
|
|
|
/* Return the return-value convention that will be used by FUNCTION
|
|
to return a value of type VALTYPE. FUNCTION may be NULL in which
|
|
case the return convention is computed based only on VALTYPE.
|
|
|
|
If READBUF is not NULL, extract the return value and save it in this buffer.
|
|
|
|
If WRITEBUF is not NULL, it contains a return value which will be
|
|
stored into the appropriate register. This can be used when we want
|
|
to force the value returned by a function (see the "return" command
|
|
for instance). */
|
|
static enum return_value_convention
|
|
z80_return_value (struct gdbarch *gdbarch, struct value *function,
|
|
struct type *valtype, struct regcache *regcache,
|
|
gdb_byte *readbuf, const gdb_byte *writebuf)
|
|
{
|
|
/* Byte are returned in L, word in HL, dword in DEHL. */
|
|
int len = TYPE_LENGTH (valtype);
|
|
|
|
if ((valtype->code () == TYPE_CODE_STRUCT
|
|
|| valtype->code () == TYPE_CODE_UNION
|
|
|| valtype->code () == TYPE_CODE_ARRAY)
|
|
&& len > 4)
|
|
return RETURN_VALUE_STRUCT_CONVENTION;
|
|
|
|
if (writebuf != NULL)
|
|
{
|
|
if (len > 2)
|
|
{
|
|
regcache->cooked_write_part (Z80_DE_REGNUM, 0, len - 2, writebuf+2);
|
|
len = 2;
|
|
}
|
|
regcache->cooked_write_part (Z80_HL_REGNUM, 0, len, writebuf);
|
|
}
|
|
|
|
if (readbuf != NULL)
|
|
{
|
|
if (len > 2)
|
|
{
|
|
regcache->cooked_read_part (Z80_DE_REGNUM, 0, len - 2, readbuf+2);
|
|
len = 2;
|
|
}
|
|
regcache->cooked_read_part (Z80_HL_REGNUM, 0, len, readbuf);
|
|
}
|
|
|
|
return RETURN_VALUE_REGISTER_CONVENTION;
|
|
}
|
|
|
|
/* function unwinds current stack frame and returns next one */
|
|
static struct z80_unwind_cache *
|
|
z80_frame_unwind_cache (struct frame_info *this_frame,
|
|
void **this_prologue_cache)
|
|
{
|
|
CORE_ADDR start_pc, current_pc;
|
|
ULONGEST this_base;
|
|
int i;
|
|
gdb_byte buf[sizeof(void*)];
|
|
struct z80_unwind_cache *info;
|
|
struct gdbarch *gdbarch = get_frame_arch (this_frame);
|
|
z80_gdbarch_tdep *tdep = (z80_gdbarch_tdep *) gdbarch_tdep (gdbarch);
|
|
int addr_len = tdep->addr_length;
|
|
|
|
if (*this_prologue_cache)
|
|
return (struct z80_unwind_cache *) *this_prologue_cache;
|
|
|
|
info = FRAME_OBSTACK_ZALLOC (struct z80_unwind_cache);
|
|
memset (info, 0, sizeof (*info));
|
|
info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
|
|
*this_prologue_cache = info;
|
|
|
|
start_pc = get_frame_func (this_frame);
|
|
current_pc = get_frame_pc (this_frame);
|
|
if ((start_pc > 0) && (start_pc <= current_pc))
|
|
z80_scan_prologue (get_frame_arch (this_frame),
|
|
start_pc, current_pc, info);
|
|
|
|
if (info->prologue_type.fp_sdcc)
|
|
{
|
|
/* With SDCC standard prologue, IX points to the end of current frame
|
|
(where previous frame pointer and state are saved). */
|
|
this_base = get_frame_register_unsigned (this_frame, Z80_IX_REGNUM);
|
|
info->prev_sp = this_base + info->size;
|
|
}
|
|
else
|
|
{
|
|
CORE_ADDR addr;
|
|
CORE_ADDR sp;
|
|
CORE_ADDR sp_mask = (1 << gdbarch_ptr_bit(gdbarch)) - 1;
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
|
/* Assume that the FP is this frame's SP but with that pushed
|
|
stack space added back. */
|
|
this_base = get_frame_register_unsigned (this_frame, Z80_SP_REGNUM);
|
|
sp = this_base + info->size;
|
|
for (;; ++sp)
|
|
{
|
|
sp &= sp_mask;
|
|
if (sp < this_base)
|
|
{ /* overflow, looks like end of stack */
|
|
sp = this_base + info->size;
|
|
break;
|
|
}
|
|
/* find return address */
|
|
read_memory (sp, buf, addr_len);
|
|
addr = extract_unsigned_integer(buf, addr_len, byte_order);
|
|
read_memory (addr-addr_len-1, buf, addr_len+1);
|
|
if (buf[0] == 0xcd || (buf[0] & 0307) == 0304) /* Is it CALL */
|
|
{ /* CALL nn or CALL cc,nn */
|
|
static const char *names[] =
|
|
{
|
|
"__sdcc_call_ix", "__sdcc_call_iy", "__sdcc_call_hl"
|
|
};
|
|
addr = extract_unsigned_integer(buf+1, addr_len, byte_order);
|
|
if (addr == start_pc)
|
|
break; /* found */
|
|
for (i = sizeof(names)/sizeof(*names)-1; i >= 0; --i)
|
|
{
|
|
struct bound_minimal_symbol msymbol;
|
|
msymbol = lookup_minimal_symbol (names[i], NULL, NULL);
|
|
if (!msymbol.minsym)
|
|
continue;
|
|
if (addr == msymbol.value_address ())
|
|
break;
|
|
}
|
|
if (i >= 0)
|
|
break;
|
|
continue;
|
|
}
|
|
else
|
|
continue; /* it is not call_nn, call_cc_nn */
|
|
}
|
|
info->prev_sp = sp;
|
|
}
|
|
|
|
/* Adjust all the saved registers so that they contain addresses and not
|
|
offsets. */
|
|
for (i = 0; i < gdbarch_num_regs (gdbarch) - 1; i++)
|
|
if (info->saved_regs[i].addr () > 0)
|
|
info->saved_regs[i].set_addr
|
|
(info->prev_sp - info->saved_regs[i].addr () * addr_len);
|
|
|
|
/* Except for the startup code, the return PC is always saved on
|
|
the stack and is at the base of the frame. */
|
|
info->saved_regs[Z80_PC_REGNUM].set_addr (info->prev_sp);
|
|
|
|
/* The previous frame's SP needed to be computed. Save the computed
|
|
value. */
|
|
info->saved_regs[Z80_SP_REGNUM].set_value (info->prev_sp + addr_len);
|
|
return info;
|
|
}
|
|
|
|
/* Given a GDB frame, determine the address of the calling function's
|
|
frame. This will be used to create a new GDB frame struct. */
|
|
static void
|
|
z80_frame_this_id (struct frame_info *this_frame, void **this_cache,
|
|
struct frame_id *this_id)
|
|
{
|
|
struct frame_id id;
|
|
struct z80_unwind_cache *info;
|
|
CORE_ADDR base;
|
|
CORE_ADDR func;
|
|
|
|
/* The FUNC is easy. */
|
|
func = get_frame_func (this_frame);
|
|
|
|
info = z80_frame_unwind_cache (this_frame, this_cache);
|
|
/* Hopefully the prologue analysis either correctly determined the
|
|
frame's base (which is the SP from the previous frame), or set
|
|
that base to "NULL". */
|
|
base = info->prev_sp;
|
|
if (base == 0)
|
|
return;
|
|
|
|
id = frame_id_build (base, func);
|
|
*this_id = id;
|
|
}
|
|
|
|
static struct value *
|
|
z80_frame_prev_register (struct frame_info *this_frame,
|
|
void **this_prologue_cache, int regnum)
|
|
{
|
|
struct z80_unwind_cache *info
|
|
= z80_frame_unwind_cache (this_frame, this_prologue_cache);
|
|
|
|
if (regnum == Z80_PC_REGNUM)
|
|
{
|
|
if (info->saved_regs[Z80_PC_REGNUM].is_addr ())
|
|
{
|
|
/* Reading the return PC from the PC register is slightly
|
|
abnormal. */
|
|
ULONGEST pc;
|
|
gdb_byte buf[3];
|
|
struct gdbarch *gdbarch = get_frame_arch (this_frame);
|
|
z80_gdbarch_tdep *tdep = (z80_gdbarch_tdep *) gdbarch_tdep (gdbarch);
|
|
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
|
|
|
read_memory (info->saved_regs[Z80_PC_REGNUM].addr (),
|
|
buf, tdep->addr_length);
|
|
pc = extract_unsigned_integer (buf, tdep->addr_length, byte_order);
|
|
return frame_unwind_got_constant (this_frame, regnum, pc);
|
|
}
|
|
|
|
return frame_unwind_got_optimized (this_frame, regnum);
|
|
}
|
|
|
|
return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
|
|
}
|
|
|
|
/* Return the breakpoint kind for this target based on *PCPTR. */
|
|
static int
|
|
z80_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
|
|
{
|
|
static int addr = -1;
|
|
if (addr == -1)
|
|
{
|
|
struct bound_minimal_symbol bh;
|
|
bh = lookup_minimal_symbol ("_break_handler", NULL, NULL);
|
|
if (bh.minsym)
|
|
addr = bh.value_address ();
|
|
else
|
|
{
|
|
warning(_("Unable to determine inferior's software breakpoint type: "
|
|
"couldn't find `_break_handler' function in inferior. Will "
|
|
"be used default software breakpoint instruction RST 0x08."));
|
|
addr = 0x0008;
|
|
}
|
|
}
|
|
return addr;
|
|
}
|
|
|
|
/* Return the software breakpoint from KIND. KIND is just address of breakpoint
|
|
handler. If address is on of standard RSTs, then RST n instruction is used
|
|
as breakpoint.
|
|
SIZE is set to the software breakpoint's length in memory. */
|
|
static const gdb_byte *
|
|
z80_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
|
|
{
|
|
static gdb_byte break_insn[8];
|
|
|
|
if ((kind & 070) == kind)
|
|
{
|
|
break_insn[0] = kind | 0307;
|
|
*size = 1;
|
|
}
|
|
else /* kind is non-RST address, use CALL instead, but it is dungerous */
|
|
{
|
|
z80_gdbarch_tdep *tdep = (z80_gdbarch_tdep *) gdbarch_tdep (gdbarch);
|
|
gdb_byte *p = break_insn;
|
|
*p++ = 0xcd;
|
|
*p++ = (kind >> 0) & 0xff;
|
|
*p++ = (kind >> 8) & 0xff;
|
|
if (tdep->addr_length > 2)
|
|
*p++ = (kind >> 16) & 0xff;
|
|
*size = p - break_insn;
|
|
}
|
|
return break_insn;
|
|
}
|
|
|
|
/* Return a vector of addresses on which the software single step
|
|
breakpoints should be inserted. NULL means software single step is
|
|
not used.
|
|
Only one breakpoint address will be returned: conditional branches
|
|
will be always evaluated. */
|
|
static std::vector<CORE_ADDR>
|
|
z80_software_single_step (struct regcache *regcache)
|
|
{
|
|
static const int flag_mask[] = {1 << 6, 1 << 0, 1 << 2, 1 << 7};
|
|
gdb_byte buf[8];
|
|
ULONGEST t;
|
|
ULONGEST addr;
|
|
int opcode;
|
|
int size;
|
|
const struct insn_info *info;
|
|
std::vector<CORE_ADDR> ret (1);
|
|
struct gdbarch *gdbarch = target_gdbarch ();
|
|
|
|
regcache->cooked_read (Z80_PC_REGNUM, &addr);
|
|
read_memory (addr, buf, sizeof(buf));
|
|
info = z80_get_insn_info (gdbarch, buf, &size);
|
|
ret[0] = addr + size;
|
|
if (info == NULL) /* possible in case of double prefix */
|
|
{ /* forced NOP, TODO: replace by NOP */
|
|
return ret;
|
|
}
|
|
opcode = buf[size - info->size]; /* take opcode instead of prefix */
|
|
/* stage 1: check for conditions */
|
|
switch (info->type)
|
|
{
|
|
case insn_djnz_d:
|
|
regcache->cooked_read (Z80_BC_REGNUM, &t);
|
|
if ((t & 0xff00) != 0x100)
|
|
return ret;
|
|
break;
|
|
case insn_jr_cc_d:
|
|
opcode &= 030; /* JR NZ,d has cc equal to 040, but others 000 */
|
|
/* fall through */
|
|
case insn_jp_cc_nn:
|
|
case insn_call_cc_nn:
|
|
case insn_ret_cc:
|
|
regcache->cooked_read (Z80_AF_REGNUM, &t);
|
|
/* lower bit of condition inverts match, so invert flags if set */
|
|
if ((opcode & 010) != 0)
|
|
t = ~t;
|
|
/* two higher bits of condition field defines flag, so use them only
|
|
to check condition of "not execute" */
|
|
if (t & flag_mask[(opcode >> 4) & 3])
|
|
return ret;
|
|
break;
|
|
}
|
|
/* stage 2: compute address */
|
|
/* TODO: implement eZ80 MADL support */
|
|
switch (info->type)
|
|
{
|
|
default:
|
|
return ret;
|
|
case insn_djnz_d:
|
|
case insn_jr_d:
|
|
case insn_jr_cc_d:
|
|
addr += size;
|
|
addr += (signed char)buf[size-1];
|
|
break;
|
|
case insn_jp_rr:
|
|
if (size == 1)
|
|
opcode = Z80_HL_REGNUM;
|
|
else
|
|
opcode = (buf[size-2] & 0x20) ? Z80_IY_REGNUM : Z80_IX_REGNUM;
|
|
regcache->cooked_read (opcode, &addr);
|
|
break;
|
|
case insn_jp_nn:
|
|
case insn_jp_cc_nn:
|
|
case insn_call_nn:
|
|
case insn_call_cc_nn:
|
|
addr = buf[size-1] * 0x100 + buf[size-2];
|
|
if (info->size > 3) /* long instruction mode */
|
|
addr = addr * 0x100 + buf[size-3];
|
|
break;
|
|
case insn_rst_n:
|
|
addr = opcode & 070;
|
|
break;
|
|
case insn_ret:
|
|
case insn_ret_cc:
|
|
regcache->cooked_read (Z80_SP_REGNUM, &addr);
|
|
read_memory (addr, buf, 3);
|
|
addr = buf[1] * 0x100 + buf[0];
|
|
if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_ez80_adl)
|
|
addr = addr * 0x100 + buf[2];
|
|
break;
|
|
}
|
|
ret[0] = addr;
|
|
return ret;
|
|
}
|
|
|
|
/* Cached, dynamically allocated copies of the target data structures: */
|
|
static unsigned (*cache_ovly_region_table)[3] = 0;
|
|
static unsigned cache_novly_regions;
|
|
static CORE_ADDR cache_ovly_region_table_base = 0;
|
|
enum ovly_index
|
|
{
|
|
VMA, OSIZE, MAPPED_TO_LMA
|
|
};
|
|
|
|
static void
|
|
z80_free_overlay_region_table (void)
|
|
{
|
|
if (cache_ovly_region_table)
|
|
xfree (cache_ovly_region_table);
|
|
cache_novly_regions = 0;
|
|
cache_ovly_region_table = NULL;
|
|
cache_ovly_region_table_base = 0;
|
|
}
|
|
|
|
/* Read an array of ints of size SIZE from the target into a local buffer.
|
|
Convert to host order. LEN is number of ints. */
|
|
|
|
static void
|
|
read_target_long_array (CORE_ADDR memaddr, unsigned int *myaddr,
|
|
int len, int size, enum bfd_endian byte_order)
|
|
{
|
|
/* alloca is safe here, because regions array is very small. */
|
|
gdb_byte *buf = (gdb_byte *) alloca (len * size);
|
|
int i;
|
|
|
|
read_memory (memaddr, buf, len * size);
|
|
for (i = 0; i < len; i++)
|
|
myaddr[i] = extract_unsigned_integer (size * i + buf, size, byte_order);
|
|
}
|
|
|
|
static int
|
|
z80_read_overlay_region_table ()
|
|
{
|
|
struct bound_minimal_symbol novly_regions_msym;
|
|
struct bound_minimal_symbol ovly_region_table_msym;
|
|
struct gdbarch *gdbarch;
|
|
int word_size;
|
|
enum bfd_endian byte_order;
|
|
|
|
z80_free_overlay_region_table ();
|
|
novly_regions_msym = lookup_minimal_symbol ("_novly_regions", NULL, NULL);
|
|
if (! novly_regions_msym.minsym)
|
|
{
|
|
error (_("Error reading inferior's overlay table: "
|
|
"couldn't find `_novly_regions'\n"
|
|
"variable in inferior. Use `overlay manual' mode."));
|
|
return 0;
|
|
}
|
|
|
|
ovly_region_table_msym = lookup_bound_minimal_symbol ("_ovly_region_table");
|
|
if (! ovly_region_table_msym.minsym)
|
|
{
|
|
error (_("Error reading inferior's overlay table: couldn't find "
|
|
"`_ovly_region_table'\n"
|
|
"array in inferior. Use `overlay manual' mode."));
|
|
return 0;
|
|
}
|
|
|
|
const enum overlay_debugging_state save_ovly_dbg = overlay_debugging;
|
|
/* prevent infinite recurse */
|
|
overlay_debugging = ovly_off;
|
|
|
|
gdbarch = ovly_region_table_msym.objfile->arch ();
|
|
word_size = gdbarch_long_bit (gdbarch) / TARGET_CHAR_BIT;
|
|
byte_order = gdbarch_byte_order (gdbarch);
|
|
|
|
cache_novly_regions = read_memory_integer (novly_regions_msym.value_address (),
|
|
4, byte_order);
|
|
cache_ovly_region_table
|
|
= (unsigned int (*)[3]) xmalloc (cache_novly_regions *
|
|
sizeof (*cache_ovly_region_table));
|
|
cache_ovly_region_table_base
|
|
= ovly_region_table_msym.value_address ();
|
|
read_target_long_array (cache_ovly_region_table_base,
|
|
(unsigned int *) cache_ovly_region_table,
|
|
cache_novly_regions * 3, word_size, byte_order);
|
|
|
|
overlay_debugging = save_ovly_dbg;
|
|
return 1; /* SUCCESS */
|
|
}
|
|
|
|
static int
|
|
z80_overlay_update_1 (struct obj_section *osect)
|
|
{
|
|
int i;
|
|
asection *bsect = osect->the_bfd_section;
|
|
unsigned lma;
|
|
unsigned vma = bfd_section_vma (bsect);
|
|
|
|
/* find region corresponding to the section VMA */
|
|
for (i = 0; i < cache_novly_regions; i++)
|
|
if (cache_ovly_region_table[i][VMA] == vma)
|
|
break;
|
|
if (i == cache_novly_regions)
|
|
return 0; /* no such region */
|
|
|
|
lma = cache_ovly_region_table[i][MAPPED_TO_LMA];
|
|
i = 0;
|
|
|
|
/* we have interest for sections with same VMA */
|
|
for (objfile *objfile : current_program_space->objfiles ())
|
|
ALL_OBJFILE_OSECTIONS (objfile, osect)
|
|
if (section_is_overlay (osect))
|
|
{
|
|
osect->ovly_mapped = (lma == bfd_section_lma (osect->the_bfd_section));
|
|
i |= osect->ovly_mapped; /* true, if at least one section is mapped */
|
|
}
|
|
return i;
|
|
}
|
|
|
|
/* Refresh overlay mapped state for section OSECT. */
|
|
static void
|
|
z80_overlay_update (struct obj_section *osect)
|
|
{
|
|
/* Always need to read the entire table anew. */
|
|
if (!z80_read_overlay_region_table ())
|
|
return;
|
|
|
|
/* Were we given an osect to look up? NULL means do all of them. */
|
|
if (osect != nullptr && z80_overlay_update_1 (osect))
|
|
return;
|
|
|
|
/* Update all sections, even if only one was requested. */
|
|
for (objfile *objfile : current_program_space->objfiles ())
|
|
ALL_OBJFILE_OSECTIONS (objfile, osect)
|
|
{
|
|
if (!section_is_overlay (osect))
|
|
continue;
|
|
|
|
asection *bsect = osect->the_bfd_section;
|
|
bfd_vma lma = bfd_section_lma (bsect);
|
|
bfd_vma vma = bfd_section_vma (bsect);
|
|
|
|
for (int i = 0; i < cache_novly_regions; ++i)
|
|
if (cache_ovly_region_table[i][VMA] == vma)
|
|
osect->ovly_mapped =
|
|
(cache_ovly_region_table[i][MAPPED_TO_LMA] == lma);
|
|
}
|
|
}
|
|
|
|
/* Return non-zero if the instruction at ADDR is a call; zero otherwise. */
|
|
static int
|
|
z80_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
|
|
{
|
|
gdb_byte buf[8];
|
|
int size;
|
|
const struct insn_info *info;
|
|
read_memory (addr, buf, sizeof(buf));
|
|
info = z80_get_insn_info (gdbarch, buf, &size);
|
|
if (info)
|
|
switch (info->type)
|
|
{
|
|
case insn_call_nn:
|
|
case insn_call_cc_nn:
|
|
case insn_rst_n:
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Return non-zero if the instruction at ADDR is a return; zero otherwise. */
|
|
static int
|
|
z80_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
|
|
{
|
|
gdb_byte buf[8];
|
|
int size;
|
|
const struct insn_info *info;
|
|
read_memory (addr, buf, sizeof(buf));
|
|
info = z80_get_insn_info (gdbarch, buf, &size);
|
|
if (info)
|
|
switch (info->type)
|
|
{
|
|
case insn_ret:
|
|
case insn_ret_cc:
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Return non-zero if the instruction at ADDR is a jump; zero otherwise. */
|
|
static int
|
|
z80_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
|
|
{
|
|
gdb_byte buf[8];
|
|
int size;
|
|
const struct insn_info *info;
|
|
read_memory (addr, buf, sizeof(buf));
|
|
info = z80_get_insn_info (gdbarch, buf, &size);
|
|
if (info)
|
|
switch (info->type)
|
|
{
|
|
case insn_jp_nn:
|
|
case insn_jp_cc_nn:
|
|
case insn_jp_rr:
|
|
case insn_jr_d:
|
|
case insn_jr_cc_d:
|
|
case insn_djnz_d:
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static const struct frame_unwind
|
|
z80_frame_unwind =
|
|
{
|
|
"z80",
|
|
NORMAL_FRAME,
|
|
default_frame_unwind_stop_reason,
|
|
z80_frame_this_id,
|
|
z80_frame_prev_register,
|
|
NULL, /*unwind_data*/
|
|
default_frame_sniffer
|
|
/*dealloc_cache*/
|
|
/*prev_arch*/
|
|
};
|
|
|
|
/* Initialize the gdbarch struct for the Z80 arch */
|
|
static struct gdbarch *
|
|
z80_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
|
{
|
|
struct gdbarch *gdbarch;
|
|
struct gdbarch_list *best_arch;
|
|
tdesc_arch_data_up tdesc_data;
|
|
unsigned long mach = info.bfd_arch_info->mach;
|
|
const struct target_desc *tdesc = info.target_desc;
|
|
|
|
if (!tdesc_has_registers (tdesc))
|
|
/* Pick a default target description. */
|
|
tdesc = tdesc_z80;
|
|
|
|
/* Check any target description for validity. */
|
|
if (tdesc_has_registers (tdesc))
|
|
{
|
|
const struct tdesc_feature *feature;
|
|
int valid_p;
|
|
|
|
feature = tdesc_find_feature (tdesc, "org.gnu.gdb.z80.cpu");
|
|
if (feature == NULL)
|
|
return NULL;
|
|
|
|
tdesc_data = tdesc_data_alloc ();
|
|
|
|
valid_p = 1;
|
|
|
|
for (unsigned i = 0; i < Z80_NUM_REGS; i++)
|
|
valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i,
|
|
z80_reg_names[i]);
|
|
|
|
if (!valid_p)
|
|
return NULL;
|
|
}
|
|
|
|
/* If there is already a candidate, use it. */
|
|
for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
|
|
best_arch != NULL;
|
|
best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
|
|
{
|
|
if (mach == gdbarch_bfd_arch_info (best_arch->gdbarch)->mach)
|
|
return best_arch->gdbarch;
|
|
}
|
|
|
|
/* None found, create a new architecture from the information provided. */
|
|
z80_gdbarch_tdep *tdep = new z80_gdbarch_tdep;
|
|
gdbarch = gdbarch_alloc (&info, tdep);
|
|
|
|
if (mach == bfd_mach_ez80_adl)
|
|
{
|
|
tdep->addr_length = 3;
|
|
set_gdbarch_max_insn_length (gdbarch, 6);
|
|
}
|
|
else
|
|
{
|
|
tdep->addr_length = 2;
|
|
set_gdbarch_max_insn_length (gdbarch, 4);
|
|
}
|
|
|
|
/* Create a type for PC. We can't use builtin types here, as they may not
|
|
be defined. */
|
|
tdep->void_type = arch_type (gdbarch, TYPE_CODE_VOID, TARGET_CHAR_BIT,
|
|
"void");
|
|
tdep->func_void_type = make_function_type (tdep->void_type, NULL);
|
|
tdep->pc_type = arch_pointer_type (gdbarch,
|
|
tdep->addr_length * TARGET_CHAR_BIT,
|
|
NULL, tdep->func_void_type);
|
|
|
|
set_gdbarch_short_bit (gdbarch, TARGET_CHAR_BIT);
|
|
set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT);
|
|
set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
|
|
set_gdbarch_ptr_bit (gdbarch, tdep->addr_length * TARGET_CHAR_BIT);
|
|
set_gdbarch_addr_bit (gdbarch, tdep->addr_length * TARGET_CHAR_BIT);
|
|
|
|
set_gdbarch_num_regs (gdbarch, (mach == bfd_mach_ez80_adl) ? EZ80_NUM_REGS
|
|
: Z80_NUM_REGS);
|
|
set_gdbarch_sp_regnum (gdbarch, Z80_SP_REGNUM);
|
|
set_gdbarch_pc_regnum (gdbarch, Z80_PC_REGNUM);
|
|
|
|
set_gdbarch_register_name (gdbarch, z80_register_name);
|
|
set_gdbarch_register_type (gdbarch, z80_register_type);
|
|
|
|
/* TODO: get FP type from binary (extra flags required) */
|
|
set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
|
|
set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
|
|
set_gdbarch_long_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
|
|
set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
|
|
set_gdbarch_double_format (gdbarch, floatformats_ieee_single);
|
|
set_gdbarch_long_double_format (gdbarch, floatformats_ieee_single);
|
|
|
|
set_gdbarch_return_value (gdbarch, z80_return_value);
|
|
|
|
set_gdbarch_skip_prologue (gdbarch, z80_skip_prologue);
|
|
set_gdbarch_inner_than (gdbarch, core_addr_lessthan); // falling stack
|
|
|
|
set_gdbarch_software_single_step (gdbarch, z80_software_single_step);
|
|
set_gdbarch_breakpoint_kind_from_pc (gdbarch, z80_breakpoint_kind_from_pc);
|
|
set_gdbarch_sw_breakpoint_from_kind (gdbarch, z80_sw_breakpoint_from_kind);
|
|
set_gdbarch_insn_is_call (gdbarch, z80_insn_is_call);
|
|
set_gdbarch_insn_is_jump (gdbarch, z80_insn_is_jump);
|
|
set_gdbarch_insn_is_ret (gdbarch, z80_insn_is_ret);
|
|
|
|
set_gdbarch_overlay_update (gdbarch, z80_overlay_update);
|
|
|
|
frame_unwind_append_unwinder (gdbarch, &z80_frame_unwind);
|
|
if (tdesc_data)
|
|
tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data));
|
|
|
|
return gdbarch;
|
|
}
|
|
|
|
/* Table to disassemble machine codes without prefix. */
|
|
static const struct insn_info
|
|
ez80_main_insn_table[] =
|
|
{ /* table with double prefix check */
|
|
{ 0100, 0377, 0, insn_force_nop}, //double prefix
|
|
{ 0111, 0377, 0, insn_force_nop}, //double prefix
|
|
{ 0122, 0377, 0, insn_force_nop}, //double prefix
|
|
{ 0133, 0377, 0, insn_force_nop}, //double prefix
|
|
/* initial table for eZ80_z80 */
|
|
{ 0100, 0377, 1, insn_z80 }, //eZ80 mode prefix
|
|
{ 0111, 0377, 1, insn_z80 }, //eZ80 mode prefix
|
|
{ 0122, 0377, 1, insn_adl }, //eZ80 mode prefix
|
|
{ 0133, 0377, 1, insn_adl }, //eZ80 mode prefix
|
|
/* here common Z80/Z180/eZ80 opcodes */
|
|
{ 0000, 0367, 1, insn_default }, //"nop", "ex af,af'"
|
|
{ 0061, 0377, 3, insn_ld_sp_nn }, //"ld sp,nn"
|
|
{ 0001, 0317, 3, insn_default }, //"ld rr,nn"
|
|
{ 0002, 0347, 1, insn_default }, //"ld (rr),a", "ld a,(rr)"
|
|
{ 0042, 0347, 3, insn_default }, //"ld (nn),hl/a", "ld hl/a,(nn)"
|
|
{ 0063, 0377, 1, insn_inc_sp }, //"inc sp"
|
|
{ 0073, 0377, 1, insn_dec_sp }, //"dec sp"
|
|
{ 0003, 0303, 1, insn_default }, //"inc rr", "dec rr", ...
|
|
{ 0004, 0307, 1, insn_default }, //"inc/dec r/(hl)"
|
|
{ 0006, 0307, 2, insn_default }, //"ld r,n", "ld (hl),n"
|
|
{ 0020, 0377, 2, insn_djnz_d }, //"djnz dis"
|
|
{ 0030, 0377, 2, insn_jr_d }, //"jr dis"
|
|
{ 0040, 0347, 2, insn_jr_cc_d }, //"jr cc,dis"
|
|
{ 0100, 0300, 1, insn_default }, //"ld r,r", "halt"
|
|
{ 0200, 0300, 1, insn_default }, //"alu_op a,r"
|
|
{ 0300, 0307, 1, insn_ret_cc }, //"ret cc"
|
|
{ 0301, 0317, 1, insn_pop_rr }, //"pop rr"
|
|
{ 0302, 0307, 3, insn_jp_cc_nn }, //"jp cc,nn"
|
|
{ 0303, 0377, 3, insn_jp_nn }, //"jp nn"
|
|
{ 0304, 0307, 3, insn_call_cc_nn}, //"call cc,nn"
|
|
{ 0305, 0317, 1, insn_push_rr }, //"push rr"
|
|
{ 0306, 0307, 2, insn_default }, //"alu_op a,n"
|
|
{ 0307, 0307, 1, insn_rst_n }, //"rst n"
|
|
{ 0311, 0377, 1, insn_ret }, //"ret"
|
|
{ 0313, 0377, 2, insn_default }, //CB prefix
|
|
{ 0315, 0377, 3, insn_call_nn }, //"call nn"
|
|
{ 0323, 0367, 2, insn_default }, //"out (n),a", "in a,(n)"
|
|
{ 0335, 0337, 1, insn_z80_ddfd }, //DD/FD prefix
|
|
{ 0351, 0377, 1, insn_jp_rr }, //"jp (hl)"
|
|
{ 0355, 0377, 1, insn_z80_ed }, //ED prefix
|
|
{ 0371, 0377, 1, insn_ld_sp_rr }, //"ld sp,hl"
|
|
{ 0000, 0000, 1, insn_default } //others
|
|
} ;
|
|
|
|
static const struct insn_info
|
|
ez80_adl_main_insn_table[] =
|
|
{ /* table with double prefix check */
|
|
{ 0100, 0377, 0, insn_force_nop}, //double prefix
|
|
{ 0111, 0377, 0, insn_force_nop}, //double prefix
|
|
{ 0122, 0377, 0, insn_force_nop}, //double prefix
|
|
{ 0133, 0377, 0, insn_force_nop}, //double prefix
|
|
/* initial table for eZ80_adl */
|
|
{ 0000, 0367, 1, insn_default }, //"nop", "ex af,af'"
|
|
{ 0061, 0377, 4, insn_ld_sp_nn }, //"ld sp,Mmn"
|
|
{ 0001, 0317, 4, insn_default }, //"ld rr,Mmn"
|
|
{ 0002, 0347, 1, insn_default }, //"ld (rr),a", "ld a,(rr)"
|
|
{ 0042, 0347, 4, insn_default }, //"ld (Mmn),hl/a", "ld hl/a,(Mmn)"
|
|
{ 0063, 0377, 1, insn_inc_sp }, //"inc sp"
|
|
{ 0073, 0377, 1, insn_dec_sp }, //"dec sp"
|
|
{ 0003, 0303, 1, insn_default }, //"inc rr", "dec rr", ...
|
|
{ 0004, 0307, 1, insn_default }, //"inc/dec r/(hl)"
|
|
{ 0006, 0307, 2, insn_default }, //"ld r,n", "ld (hl),n"
|
|
{ 0020, 0377, 2, insn_djnz_d }, //"djnz dis"
|
|
{ 0030, 0377, 2, insn_jr_d }, //"jr dis"
|
|
{ 0040, 0347, 2, insn_jr_cc_d }, //"jr cc,dis"
|
|
{ 0100, 0377, 1, insn_z80 }, //eZ80 mode prefix (short instruction)
|
|
{ 0111, 0377, 1, insn_z80 }, //eZ80 mode prefix (short instruction)
|
|
{ 0122, 0377, 1, insn_adl }, //eZ80 mode prefix (long instruction)
|
|
{ 0133, 0377, 1, insn_adl }, //eZ80 mode prefix (long instruction)
|
|
{ 0100, 0300, 1, insn_default }, //"ld r,r", "halt"
|
|
{ 0200, 0300, 1, insn_default }, //"alu_op a,r"
|
|
{ 0300, 0307, 1, insn_ret_cc }, //"ret cc"
|
|
{ 0301, 0317, 1, insn_pop_rr }, //"pop rr"
|
|
{ 0302, 0307, 4, insn_jp_cc_nn }, //"jp cc,nn"
|
|
{ 0303, 0377, 4, insn_jp_nn }, //"jp nn"
|
|
{ 0304, 0307, 4, insn_call_cc_nn}, //"call cc,Mmn"
|
|
{ 0305, 0317, 1, insn_push_rr }, //"push rr"
|
|
{ 0306, 0307, 2, insn_default }, //"alu_op a,n"
|
|
{ 0307, 0307, 1, insn_rst_n }, //"rst n"
|
|
{ 0311, 0377, 1, insn_ret }, //"ret"
|
|
{ 0313, 0377, 2, insn_default }, //CB prefix
|
|
{ 0315, 0377, 4, insn_call_nn }, //"call Mmn"
|
|
{ 0323, 0367, 2, insn_default }, //"out (n),a", "in a,(n)"
|
|
{ 0335, 0337, 1, insn_adl_ddfd }, //DD/FD prefix
|
|
{ 0351, 0377, 1, insn_jp_rr }, //"jp (hl)"
|
|
{ 0355, 0377, 1, insn_adl_ed }, //ED prefix
|
|
{ 0371, 0377, 1, insn_ld_sp_rr }, //"ld sp,hl"
|
|
{ 0000, 0000, 1, insn_default } //others
|
|
};
|
|
|
|
/* ED prefix opcodes table.
|
|
Note the instruction length does include the ED prefix (+ 1 byte)
|
|
*/
|
|
static const struct insn_info
|
|
ez80_ed_insn_table[] =
|
|
{
|
|
/* eZ80 only instructions */
|
|
{ 0002, 0366, 2, insn_default }, //"lea rr,ii+d"
|
|
{ 0124, 0376, 2, insn_default }, //"lea ix,iy+d", "lea iy,ix+d"
|
|
{ 0145, 0377, 2, insn_default }, //"pea ix+d"
|
|
{ 0146, 0377, 2, insn_default }, //"pea iy+d"
|
|
{ 0164, 0377, 2, insn_default }, //"tstio n"
|
|
/* Z180/eZ80 only instructions */
|
|
{ 0060, 0376, 1, insn_default }, //not an instruction
|
|
{ 0000, 0306, 2, insn_default }, //"in0 r,(n)", "out0 (n),r"
|
|
{ 0144, 0377, 2, insn_default }, //"tst a, n"
|
|
/* common instructions */
|
|
{ 0173, 0377, 3, insn_ld_sp_6nn9 }, //"ld sp,(nn)"
|
|
{ 0103, 0307, 3, insn_default }, //"ld (nn),rr", "ld rr,(nn)"
|
|
{ 0105, 0317, 1, insn_ret }, //"retn", "reti"
|
|
{ 0000, 0000, 1, insn_default }
|
|
};
|
|
|
|
static const struct insn_info
|
|
ez80_adl_ed_insn_table[] =
|
|
{
|
|
{ 0002, 0366, 2, insn_default }, //"lea rr,ii+d"
|
|
{ 0124, 0376, 2, insn_default }, //"lea ix,iy+d", "lea iy,ix+d"
|
|
{ 0145, 0377, 2, insn_default }, //"pea ix+d"
|
|
{ 0146, 0377, 2, insn_default }, //"pea iy+d"
|
|
{ 0164, 0377, 2, insn_default }, //"tstio n"
|
|
{ 0060, 0376, 1, insn_default }, //not an instruction
|
|
{ 0000, 0306, 2, insn_default }, //"in0 r,(n)", "out0 (n),r"
|
|
{ 0144, 0377, 2, insn_default }, //"tst a, n"
|
|
{ 0173, 0377, 4, insn_ld_sp_6nn9 }, //"ld sp,(nn)"
|
|
{ 0103, 0307, 4, insn_default }, //"ld (nn),rr", "ld rr,(nn)"
|
|
{ 0105, 0317, 1, insn_ret }, //"retn", "reti"
|
|
{ 0000, 0000, 1, insn_default }
|
|
};
|
|
|
|
/* table for FD and DD prefixed instructions */
|
|
static const struct insn_info
|
|
ez80_ddfd_insn_table[] =
|
|
{
|
|
/* ez80 only instructions */
|
|
{ 0007, 0307, 2, insn_default }, //"ld rr,(ii+d)"
|
|
{ 0061, 0377, 2, insn_default }, //"ld ii,(ii+d)"
|
|
/* common instructions */
|
|
{ 0011, 0367, 2, insn_default }, //"add ii,rr"
|
|
{ 0041, 0377, 3, insn_default }, //"ld ii,nn"
|
|
{ 0042, 0367, 3, insn_default }, //"ld (nn),ii", "ld ii,(nn)"
|
|
{ 0043, 0367, 1, insn_default }, //"inc ii", "dec ii"
|
|
{ 0044, 0366, 1, insn_default }, //"inc/dec iih/iil"
|
|
{ 0046, 0367, 2, insn_default }, //"ld iih,n", "ld iil,n"
|
|
{ 0064, 0376, 2, insn_default }, //"inc (ii+d)", "dec (ii+d)"
|
|
{ 0066, 0377, 2, insn_default }, //"ld (ii+d),n"
|
|
{ 0166, 0377, 0, insn_default }, //not an instruction
|
|
{ 0160, 0370, 2, insn_default }, //"ld (ii+d),r"
|
|
{ 0104, 0306, 1, insn_default }, //"ld r,iih", "ld r,iil"
|
|
{ 0106, 0307, 2, insn_default }, //"ld r,(ii+d)"
|
|
{ 0140, 0360, 1, insn_default }, //"ld iih,r", "ld iil,r"
|
|
{ 0204, 0306, 1, insn_default }, //"alu_op a,iih", "alu_op a,iil"
|
|
{ 0206, 0307, 2, insn_default }, //"alu_op a,(ii+d)"
|
|
{ 0313, 0377, 3, insn_default }, //DD/FD CB dd oo instructions
|
|
{ 0335, 0337, 0, insn_force_nop}, //double DD/FD prefix, exec DD/FD as NOP
|
|
{ 0341, 0373, 1, insn_default }, //"pop ii", "push ii"
|
|
{ 0343, 0377, 1, insn_default }, //"ex (sp),ii"
|
|
{ 0351, 0377, 1, insn_jp_rr }, //"jp (ii)"
|
|
{ 0371, 0377, 1, insn_ld_sp_rr}, //"ld sp,ii"
|
|
{ 0000, 0000, 0, insn_default } //not an instruction, exec DD/FD as NOP
|
|
};
|
|
|
|
static const struct insn_info
|
|
ez80_adl_ddfd_insn_table[] =
|
|
{
|
|
{ 0007, 0307, 2, insn_default }, //"ld rr,(ii+d)"
|
|
{ 0061, 0377, 2, insn_default }, //"ld ii,(ii+d)"
|
|
{ 0011, 0367, 1, insn_default }, //"add ii,rr"
|
|
{ 0041, 0377, 4, insn_default }, //"ld ii,nn"
|
|
{ 0042, 0367, 4, insn_default }, //"ld (nn),ii", "ld ii,(nn)"
|
|
{ 0043, 0367, 1, insn_default }, //"inc ii", "dec ii"
|
|
{ 0044, 0366, 1, insn_default }, //"inc/dec iih/iil"
|
|
{ 0046, 0367, 2, insn_default }, //"ld iih,n", "ld iil,n"
|
|
{ 0064, 0376, 2, insn_default }, //"inc (ii+d)", "dec (ii+d)"
|
|
{ 0066, 0377, 3, insn_default }, //"ld (ii+d),n"
|
|
{ 0166, 0377, 0, insn_default }, //not an instruction
|
|
{ 0160, 0370, 2, insn_default }, //"ld (ii+d),r"
|
|
{ 0104, 0306, 1, insn_default }, //"ld r,iih", "ld r,iil"
|
|
{ 0106, 0307, 2, insn_default }, //"ld r,(ii+d)"
|
|
{ 0140, 0360, 1, insn_default }, //"ld iih,r", "ld iil,r"
|
|
{ 0204, 0306, 1, insn_default }, //"alu_op a,iih", "alu_op a,iil"
|
|
{ 0206, 0307, 2, insn_default }, //"alu_op a,(ii+d)"
|
|
{ 0313, 0377, 3, insn_default }, //DD/FD CB dd oo instructions
|
|
{ 0335, 0337, 0, insn_force_nop}, //double DD/FD prefix, exec DD/FD as NOP
|
|
{ 0341, 0373, 1, insn_default }, //"pop ii", "push ii"
|
|
{ 0343, 0377, 1, insn_default }, //"ex (sp),ii"
|
|
{ 0351, 0377, 1, insn_jp_rr }, //"jp (ii)"
|
|
{ 0371, 0377, 1, insn_ld_sp_rr}, //"ld sp,ii"
|
|
{ 0000, 0000, 0, insn_default } //not an instruction, exec DD/FD as NOP
|
|
};
|
|
|
|
/* Return pointer to instruction information structure corresponded to opcode
|
|
in buf. */
|
|
static const struct insn_info *
|
|
z80_get_insn_info (struct gdbarch *gdbarch, const gdb_byte *buf, int *size)
|
|
{
|
|
int code;
|
|
const struct insn_info *info;
|
|
unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach;
|
|
*size = 0;
|
|
switch (mach)
|
|
{
|
|
case bfd_mach_ez80_z80:
|
|
info = &ez80_main_insn_table[4]; /* skip force_nops */
|
|
break;
|
|
case bfd_mach_ez80_adl:
|
|
info = &ez80_adl_main_insn_table[4]; /* skip force_nops */
|
|
break;
|
|
default:
|
|
info = &ez80_main_insn_table[8]; /* skip eZ80 prefices and force_nops */
|
|
break;
|
|
}
|
|
do
|
|
{
|
|
for (; ((code = buf[*size]) & info->mask) != info->code; ++info)
|
|
;
|
|
*size += info->size;
|
|
/* process instruction type */
|
|
switch (info->type)
|
|
{
|
|
case insn_z80:
|
|
if (mach == bfd_mach_ez80_z80 || mach == bfd_mach_ez80_adl)
|
|
info = &ez80_main_insn_table[0];
|
|
else
|
|
info = &ez80_main_insn_table[8];
|
|
break;
|
|
case insn_adl:
|
|
info = &ez80_adl_main_insn_table[0];
|
|
break;
|
|
/* These two (for GameBoy Z80 & Z80 Next CPUs) haven't been tested.
|
|
|
|
case bfd_mach_gbz80:
|
|
info = &gbz80_main_insn_table[0];
|
|
break;
|
|
case bfd_mach_z80n:
|
|
info = &z80n_main_insn_table[0];
|
|
break;
|
|
*/
|
|
case insn_z80_ddfd:
|
|
if (mach == bfd_mach_ez80_z80 || mach == bfd_mach_ez80_adl)
|
|
info = &ez80_ddfd_insn_table[0];
|
|
else
|
|
info = &ez80_ddfd_insn_table[2];
|
|
break;
|
|
case insn_adl_ddfd:
|
|
info = &ez80_adl_ddfd_insn_table[0];
|
|
break;
|
|
case insn_z80_ed:
|
|
info = &ez80_ed_insn_table[0];
|
|
break;
|
|
case insn_adl_ed:
|
|
info = &ez80_adl_ed_insn_table[0];
|
|
break;
|
|
case insn_force_nop:
|
|
return NULL;
|
|
default:
|
|
return info;
|
|
}
|
|
}
|
|
while (1);
|
|
}
|
|
|
|
extern initialize_file_ftype _initialize_z80_tdep;
|
|
|
|
void
|
|
_initialize_z80_tdep ()
|
|
{
|
|
register_gdbarch_init (bfd_arch_z80, z80_gdbarch_init);
|
|
initialize_tdesc_z80 ();
|
|
}
|