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https://sourceware.org/git/binutils-gdb.git
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09c1e68a16
binutils * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new
disassembly.
* testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise.
ld/ * testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly.
* testsuite/ld-aarch64/farcall-b-section.d: Likewise.
* testsuite/ld-aarch64/farcall-back.d: Likewise.
* testsuite/ld-aarch64/farcall-bl-section.d: Likewise.
gas/ * config/tc-aarch64.c (fix_insn): Implement for AARCH64_OPND_UNDEFINED.
(parse_operands): Implement for AARCH64_OPND_UNDEFINED.
* testsuite/gas/aarch64/udf.s: New.
* testsuite/gas/aarch64/udf.d: New.
* testsuite/gas/aarch64/udf-invalid.s: New.
* testsuite/gas/aarch64/udf-invalid.l: New.
* testsuite/gas/aarch64/udf-invalid.d: New.
include * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_UNDEFINED.
opcodes * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
* aarch64-opc.c (fields): Add entry for FLD_imm16_2.
(operand_general_constraint_met_p): validate AARCH64_OPND_UNDEFINED.
* aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry for
FLD_imm16_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
50 lines
1.5 KiB
Makefile
50 lines
1.5 KiB
Makefile
#source: erratum843419_tls_ie.s
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#as:
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#ld: --fix-cortex-a53-843419 -e0 --section-start .e843419=0x20000000 -Ttext=0x400000 -Tdata=0x40000000
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#objdump: -dr
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#...
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Disassembly of section .e843419:
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0*20000000 <farbranch>:
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[ ]*20000000: d10043ff sub sp, sp, #0x10
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[ ]*20000004: d28001a7 mov x7, #0xd // #13
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[ ]*20000008: b9000fe7 str w7, \[sp, #12\]
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[ ]*2000000c: 140003fb b 20000ff8 <e843419>
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...
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0*20000ff8 <e843419>:
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[ ]*20000ff8: d2a00000 movz x0, #0x0, lsl #16
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[ ]*20000ffc: f800c007 stur x7, \[x0, #12\]
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[ ]*20001000: d2800128 mov x8, #0x9 // #9
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[ ]*20001004: f2800208 movk x8, #0x10
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[ ]*20001008: 8b050020 add x0, x1, x5
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[ ]*2000100c: b9400fe7 ldr w7, \[sp, #12\]
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[ ]*20001010: 0b0700e0 add w0, w7, w7
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[ ]*20001014: 910043ff add sp, sp, #0x10
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[ ]*20001018: d65f03c0 ret
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[ ]*2000101c: 00000000 udf #0
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[ ]*20001020: 14000400 b 20002020 <e843419\+0x1028>
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[ ]*20001024: d503201f nop
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[ ]*20001028: 00000000 udf #0
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[ ]*2000102c: 17fffff7 b 20001008 <e843419\+0x10>
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...
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Disassembly of section .text:
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0*400000 <main>:
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[ ]*400000: d10043ff sub sp, sp, #0x10
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[ ]*400004: d28001a7 mov x7, #0xd // #13
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[ ]*400008: b9000fe7 str w7, \[sp, #12\]
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[ ]*40000c: 14000005 b 400020 <__farbranch_veneer>
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[ ]*400010: d65f03c0 ret
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[ ]*400014: d503201f nop
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[ ]*400018: 14000400 b 401018 <__farbranch_veneer\+0xff8>
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[ ]*40001c: d503201f nop
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0*400020 <__farbranch_veneer>:
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[ ]*400020: 900fe010 adrp x16, 20000000 <farbranch>
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[ ]*400024: 91000210 add x16, x16, #0x0
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[ ]*400028: d61f0200 br x16
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...
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