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259364adb8
The linker relaxation logic will be: Code sequence I (tiny): 0x00 adr x0, :tlsldm:x 0x04 bl __tls_get_addr | V 0x00 mrs x0, tpidr_el0 0x04 add x0, x0, TCB_SIZE Code sequence II (small): 0x00 adrp a0, :tlsldm:x 0x04 add a0, #:tlsldm_lo12:x 0x08 bl __tls_get_addr | V 0x00 mrs x0, tpidr_el0 0x04 add x0, x0, TCB_SIZE 0x08 nop 2015-09-09 Jiong Wang <jiong.wang@arm.com> bfd/ * elfnn-aarch64.c (aarch64_tls_transition_without_check): Support three TLS local dynamic traditional relocations types. (elfNN_aarch64_tls_relax): Support TLS local dynamic traditional to local executable relaxation. ld/testsuite/ * ld-aarch64/tls-relax-ld-le-tiny.s: New testcase. * ld-aarch64/tls-relax-ld-le-small.s: Likewise. * ld-aarch64/tls-relax-ld-le-tiny.d: New expectation file. * ld-aarch64/tls-relax-ld-le-small.d: Likewise. * ld-aarch64/aarch64-elf.exp: Run new testcases.
28 lines
560 B
ArmAsm
28 lines
560 B
ArmAsm
.cpu generic+fp+simd
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.section .text.startup,"ax",%progbits
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.align 2
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.p2align 3,,7
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.global main
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.type main, %function
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main:
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add x29, sp, 0
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adrp x0, :tlsldm:global_a0
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add x0, x0, #:tlsldm_lo12_nc:global_a0
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bl __tls_get_addr
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nop
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add x1, x0, #:dtprel_hi12:global_a0, lsl #12
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add x1, x1, #:dtprel_lo12_nc:global_a0
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adrp x0, .LC0
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ret
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.size main, .-main
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.section .rodata.str1.8,"aMS",%progbits,1
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.align 3
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.LC0:
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.string "Hello world %d\n"
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.section .tdata,"awT",%progbits
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.align 2
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.type global_a0, %object
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.size global_a0, 4
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global_a0:
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.word 16
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