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334 lines
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Plaintext
334 lines
9.0 KiB
Plaintext
@c Copyright 2000, 2001, 2005, 2006, 2007 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node ARC-Dependent
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@chapter ARC Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter ARC Dependent Features
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@end ifclear
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@set ARC_CORE_DEFAULT 6
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@cindex ARC support
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@menu
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* ARC Options:: Options
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* ARC Syntax:: Syntax
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* ARC Floating Point:: Floating Point
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* ARC Directives:: ARC Machine Directives
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* ARC Opcodes:: Opcodes
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@end menu
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@node ARC Options
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@section Options
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@cindex ARC options (none)
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@cindex options for ARC (none)
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@table @code
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@cindex @code{-marc[5|6|7|8]} command line option, ARC
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@item -marc[5|6|7|8]
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This option selects the core processor variant. Using
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@code{-marc} is the same as @code{-marc@value{ARC_CORE_DEFAULT}}, which
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is also the default.
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@table @code
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@cindex @code{arc5} arc5, ARC
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@item arc5
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Base instruction set.
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@cindex @code{arc6} arc6, ARC
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@item arc6
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Jump-and-link (jl) instruction. No requirement of an instruction between
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setting flags and conditional jump. For example:
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@smallexample
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mov.f r0,r1
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beq foo
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@end smallexample
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@cindex @code{arc7} arc7, ARC
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@item arc7
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Break (brk) and sleep (sleep) instructions.
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@cindex @code{arc8} arc8, ARC
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@item arc8
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Software interrupt (swi) instruction.
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@end table
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Note: the @code{.option} directive can to be used to select a core
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variant from within assembly code.
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@cindex @code{-EB} command line option, ARC
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@item -EB
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a big-endian processor.
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@cindex @code{-EL} command line option, ARC
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@item -EL
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a little-endian processor - this is the
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default.
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@end table
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@node ARC Syntax
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@section Syntax
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@menu
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* ARC-Chars:: Special Characters
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* ARC-Regs:: Register Names
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@end menu
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@node ARC-Chars
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@subsection Special Characters
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@cindex ARC special characters
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@cindex special characters, ARC
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*TODO*
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@node ARC-Regs
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@subsection Register Names
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@cindex ARC register names
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@cindex register names, ARC
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*TODO*
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@node ARC Floating Point
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@section Floating Point
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@cindex floating point, ARC (@sc{ieee})
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@cindex ARC floating point (@sc{ieee})
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The ARC core does not currently have hardware floating point
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support. Software floating point support is provided by @code{GCC}
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and uses @sc{ieee} floating-point numbers.
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@node ARC Directives
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@section ARC Machine Directives
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@cindex machine directives, ARC
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@cindex ARC machine directives
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The ARC version of @code{@value{AS}} supports the following additional
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machine directives:
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@table @code
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@cindex @code{2byte} directive, ARC
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@item .2byte @var{expressions}
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*TODO*
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@cindex @code{3byte} directive, ARC
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@item .3byte @var{expressions}
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*TODO*
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@cindex @code{4byte} directive, ARC
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@item .4byte @var{expressions}
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*TODO*
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@cindex @code{extAuxRegister} directive, ARC
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@item .extAuxRegister @var{name},@var{address},@var{mode}
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The ARCtangent A4 has extensible auxiliary register space. The
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auxiliary registers can be defined in the assembler source code by
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using this directive. The first parameter is the @var{name} of the
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new auxiallry register. The second parameter is the @var{address} of
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the register in the auxiliary register memory map for the variant of
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the ARC. The third parameter specifies the @var{mode} in which the
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register can be operated is and it can be one of:
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@table @code
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@item r (readonly)
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@item w (write only)
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@item r|w (read or write)
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@end table
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For example:
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@smallexample
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.extAuxRegister mulhi,0x12,w
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@end smallexample
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This specifies an extension auxiliary register called @emph{mulhi}
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which is at address 0x12 in the memory space and which is only
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writable.
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@cindex @code{extCondCode} directive, ARC
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@item .extCondCode @var{suffix},@var{value}
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The condition codes on the ARCtangent A4 are extensible and can be
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specified by means of this assembler directive. They are specified
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by the suffix and the value for the condition code. They can be used to
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specify extra condition codes with any values. For example:
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@smallexample
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.extCondCode is_busy,0x14
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add.is_busy r1,r2,r3
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bis_busy _main
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@end smallexample
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@cindex @code{extCoreRegister} directive, ARC
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@item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut}
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Specifies an extension core register @var{name} for the application.
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This allows a register @var{name} with a valid @var{regnum} between 0
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and 60, with the following as valid values for @var{mode}
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@table @samp
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@item @emph{r} (readonly)
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@item @emph{w} (write only)
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@item @emph{r|w} (read or write)
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@end table
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The other parameter gives a description of the register having a
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@var{shortcut} in the pipeline. The valid values are:
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@table @code
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@item can_shortcut
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@item cannot_shortcut
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@end table
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For example:
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@smallexample
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.extCoreRegister mlo,57,r,can_shortcut
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@end smallexample
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This defines an extension core register mlo with the value 57 which
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can shortcut the pipeline.
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@cindex @code{extInstruction} directive, ARC
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@item .extInstruction @var{name},@var{opcode},@var{subopcode},@var{suffixclass},@var{syntaxclass}
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The ARCtangent A4 allows the user to specify extension instructions.
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The extension instructions are not macros. The assembler creates
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encodings for use of these instructions according to the specification
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by the user. The parameters are:
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@table @bullet
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@item @var{name}
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Name of the extension instruction
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@item @var{opcode}
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Opcode to be used. (Bits 27:31 in the encoding). Valid values
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0x10-0x1f or 0x03
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@item @var{subopcode}
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Subopcode to be used. Valid values are from 0x09-0x3f. However the
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correct value also depends on @var{syntaxclass}
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@item @var{suffixclass}
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Determines the kinds of suffixes to be allowed. Valid values are
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@code{SUFFIX_NONE}, @code{SUFFIX_COND},
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@code{SUFFIX_FLAG} which indicates the absence or presence of
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conditional suffixes and flag setting by the extension instruction.
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It is also possible to specify that an instruction sets the flags and
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is conditional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}.
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@item @var{syntaxclass}
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Determines the syntax class for the instruction. It can have the
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following values:
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@table @code
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@item @code{SYNTAX_2OP}:
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2 Operand Instruction
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@item @code{SYNTAX_3OP}:
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3 Operand Instruction
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@end table
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In addition there could be modifiers for the syntax class as described
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below:
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@itemize @minus
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Syntax Class Modifiers are:
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@item @code{OP1_MUST_BE_IMM}:
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Modifies syntax class SYNTAX_3OP, specifying that the first operand
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of a three-operand instruction must be an immediate (i.e., the result
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is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with
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SYNTAX_3OP as given in the example below. This could usually be used
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to set the flags using specific instructions and not retain results.
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@item @code{OP1_IMM_IMPLIED}:
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Modifies syntax class SYNTAX_20P, it specifies that there is an
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implied immediate destination operand which does not appear in the
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syntax. For example, if the source code contains an instruction like:
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@smallexample
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inst r1,r2
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@end smallexample
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it really means that the first argument is an implied immediate (that
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is, the result is discarded). This is the same as though the source
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code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it
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with SYNTAX_20P.
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@end itemize
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@end table
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For example, defining 64-bit multiplier with immediate operands:
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@smallexample
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.extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
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SYNTAX_3OP|OP1_MUST_BE_IMM
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@end smallexample
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The above specifies an extension instruction called mp64 which has 3 operands,
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sets the flags, can be used with a condition code, for which the
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first operand is an immediate. (Equivalent to discarding the result
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of the operation).
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@smallexample
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.extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
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@end smallexample
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This describes a 2 operand instruction with an implicit first
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immediate operand. The result of this operation would be discarded.
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@cindex @code{half} directive, ARC
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@item .half @var{expressions}
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*TODO*
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@cindex @code{long} directive, ARC
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@item .long @var{expressions}
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*TODO*
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@cindex @code{option} directive, ARC
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@item .option @var{arc|arc5|arc6|arc7|arc8}
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The @code{.option} directive must be followed by the desired core
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version. Again @code{arc} is an alias for
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@code{arc@value{ARC_CORE_DEFAULT}}.
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Note: the @code{.option} directive overrides the command line option
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@code{-marc}; a warning is emitted when the version is not consistent
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between the two - even for the implicit default core version
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(arc@value{ARC_CORE_DEFAULT}).
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@cindex @code{short} directive, ARC
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@item .short @var{expressions}
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*TODO*
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@cindex @code{word} directive, ARC
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@item .word @var{expressions}
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*TODO*
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@end table
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@node ARC Opcodes
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@section Opcodes
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@cindex ARC opcodes
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@cindex opcodes for ARC
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For information on the ARC instruction set, see @cite{ARC Programmers
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Reference Manual}, ARC International (www.arc.com)
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