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d8740be159
cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64. * bpf.opc (bpf_print_insn): Do not set endian_code here. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to bpf_cgen_cpu_open. (md_assemble): Remove no longer needed hack. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * disassemble.c (disassemble_init_for_target): Set endian_code for bpf targets. * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. * bpf-dis.c: Likewise.
192 lines
4.9 KiB
C
192 lines
4.9 KiB
C
/* EBPF opcode support. -*- c -*-
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Copyright (C) 2019 Free Software Foundation, Inc.
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Contributed by Oracle, Inc.
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This file is part of the GNU Binutils and of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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/*
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Each section is delimited with start and end markers.
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<arch>-opc.h additions use: "-- opc.h"
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<arch>-opc.c additions use: "-- opc.c"
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<arch>-asm.c additions use: "-- asm.c"
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<arch>-dis.c additions use: "-- dis.c"
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<arch>-ibd.h additions use: "-- ibd.h". */
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/* -- opc.h */
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#undef CGEN_DIS_HASH_SIZE
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#define CGEN_DIS_HASH_SIZE 1
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#undef CGEN_DIS_HASH
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#define CGEN_DIS_HASH(buffer, value) 0
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/* Allows reason codes to be output when assembler errors occur. */
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#define CGEN_VERBOSE_ASSEMBLER_ERRORS
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#define CGEN_VALIDATE_INSN_SUPPORTED
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extern int bpf_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
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/* -- opc.c */
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/* -- asm.c */
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/* Parse a signed 64-bit immediate. */
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static const char *
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parse_imm64 (CGEN_CPU_DESC cd,
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const char **strp,
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int opindex,
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int64_t *valuep)
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{
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bfd_vma value;
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enum cgen_parse_operand_result result;
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const char *errmsg;
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errmsg = (* cd->parse_operand_fn)
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(cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE,
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&result, &value);
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if (!errmsg)
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*valuep = value;
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return errmsg;
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}
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/* Endianness size operands are integer immediates whose values can be
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16, 32 or 64. */
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static const char *
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parse_endsize (CGEN_CPU_DESC cd,
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const char **strp,
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int opindex,
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unsigned long *valuep)
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{
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const char *errmsg;
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errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
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if (errmsg)
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return errmsg;
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switch (*valuep)
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{
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case 16:
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case 32:
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case 64:
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break;
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default:
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return _("expected 16, 32 or 64 in");
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}
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return NULL;
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}
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/* Special check to ensure that the right instruction variant is used
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for the given endianness induced by the ISA selected in the CPU.
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See bpf.cpu for a discussion on how eBPF is really two instruction
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sets. */
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int
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bpf_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
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{
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CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
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return cgen_bitset_intersect_p (&isas, cd->isas);
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}
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/* -- dis.c */
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/* We need to customize the disassembler a bit:
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- Use 8 bytes per line by default.
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*/
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#define CGEN_PRINT_INSN bpf_print_insn
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static int
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bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
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{
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bfd_byte buf[CGEN_MAX_INSN_SIZE];
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int buflen;
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int status;
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info->bytes_per_chunk = 1;
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info->bytes_per_line = 8;
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/* Attempt to read the base part of the insn. */
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buflen = cd->base_insn_bitsize / 8;
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status = (*info->read_memory_func) (pc, buf, buflen, info);
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/* Try again with the minimum part, if min < base. */
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if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
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{
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buflen = cd->min_insn_bitsize / 8;
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status = (*info->read_memory_func) (pc, buf, buflen, info);
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}
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if (status != 0)
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{
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(*info->memory_error_func) (status, pc, info);
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return -1;
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}
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return print_insn (cd, pc, info, buf, buflen);
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}
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/* Signed immediates should be printed in hexadecimal. */
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static void
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print_immediate (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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void *dis_info,
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int64_t value,
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unsigned int attrs ATTRIBUTE_UNUSED,
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bfd_vma pc ATTRIBUTE_UNUSED,
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int length ATTRIBUTE_UNUSED)
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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if (value <= 9)
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(*info->fprintf_func) (info->stream, "%" PRId64, value);
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else
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(*info->fprintf_func) (info->stream, "%#" PRIx64, value);
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/* This is to avoid -Wunused-function for print_normal. */
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if (0)
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print_normal (cd, dis_info, value, attrs, pc, length);
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}
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/* Endianness bit sizes should be printed in decimal. */
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static void
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print_endsize (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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void *dis_info,
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unsigned long value,
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unsigned int attrs ATTRIBUTE_UNUSED,
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bfd_vma pc ATTRIBUTE_UNUSED,
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int length ATTRIBUTE_UNUSED)
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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(*info->fprintf_func) (info->stream, "%lu", value);
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}
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/* -- */
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