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binutils-gdb/ld/testsuite/ld-riscv-elf
History
Palmer Dabbelt 87fdd7ac09
RISC-V: Stop reporting warnings for mismatched extension versions 
The extension version checking logic is really just too complicated to
encode into the linker, trying to do so causes more harm than good.
This removes the checks and the associated tests, leaving the logic to
keep the largest version of each extension linked into the target.

bfd/

	* elfnn-riscv.c (riscv_version_mismatch): Rename to
	riscv_update_subset_version, and stop reporting warnings on
	version mismatches.
	(riscv_merge_std_ext): Adjust calls to riscv_version_mismatch.
	(riscv_merge_multi_letter_ext): Likewise.

ld/
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Remove
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s: Likewise
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s: Likewise
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02a.s: Likewise
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02b.s: Likewise
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02c.s: Likewise
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02d.s: Likewise
	* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: New test.
	* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i21_m2p0.s:
	Likewise.
	* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i21_m2p1.s:
	Likewise.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Remove obselete
	attr-merge-arch-failed-{01,02}, replace with
	attr-merge-user-ext-01.

Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-02-08 08:23:28 -08:00
..
align-small-region.d RISC-V: Don't separate pcgp relaxation to another relax pass. 2021-10-22 16:44:37 +08:00
align-small-region.ld RISC-V: Don't separate pcgp relaxation to another relax pass. 2021-10-22 16:44:37 +08:00
align-small-region.s RISC-V: Don't separate pcgp relaxation to another relax pass. 2021-10-22 16:44:37 +08:00
attr-merge-arch-01.d RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-01a.s RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-01b.s RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-02.d RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-02a.s RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-02b.s RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-03.d RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-03a.s RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-arch-03b.s RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
attr-merge-priv-spec-01.d
attr-merge-priv-spec-02.d
attr-merge-priv-spec-03.d
attr-merge-priv-spec-a.s
attr-merge-priv-spec-b.s
attr-merge-priv-spec-c.s
attr-merge-priv-spec-d.s
attr-merge-priv-spec-failed-01.d
attr-merge-priv-spec-failed-02.d
attr-merge-priv-spec-failed-03.d
attr-merge-priv-spec-failed-04.d
attr-merge-priv-spec-failed-05.d
attr-merge-priv-spec-failed-06.d
attr-merge-stack-align-a.s
attr-merge-stack-align-b.s
attr-merge-stack-align-failed-a.s
attr-merge-stack-align-failed-b.s
attr-merge-stack-align-failed.d
attr-merge-stack-align.d
attr-merge-strict-align-01.d
attr-merge-strict-align-01a.s
attr-merge-strict-align-01b.s
attr-merge-strict-align-02.d
attr-merge-strict-align-02a.s
attr-merge-strict-align-02b.s
attr-merge-strict-align-03.d
attr-merge-strict-align-03a.s
attr-merge-strict-align-03b.s
attr-merge-strict-align-04.d
attr-merge-strict-align-04a.s
attr-merge-strict-align-04b.s
attr-merge-strict-align-05.d
attr-merge-strict-align-05a.s
attr-merge-strict-align-05b.s
attr-merge-user-ext-01.d RISC-V: Stop reporting warnings for mismatched extension versions 2022-02-08 08:23:28 -08:00
attr-merge-user-ext-rv32i2p1_m2p0.s RISC-V: Stop reporting warnings for mismatched extension versions 2022-02-08 08:23:28 -08:00
attr-merge-user-ext-rv32i2p1_m2p1.s RISC-V: Stop reporting warnings for mismatched extension versions 2022-02-08 08:23:28 -08:00
attr-phdr.d RISC-V: Add PT_RISCV_ATTRIBUTES and add it to PHDR. 2021-07-06 11:34:36 +08:00
attr-phdr.s RISC-V: Add PT_RISCV_ATTRIBUTES and add it to PHDR. 2021-07-06 11:34:36 +08:00
c-lui-2.d
c-lui-2.ld
c-lui-2.s
c-lui.d
c-lui.s
call-relax-0.s
call-relax-1.s
call-relax-2.s
call-relax-3.s
call-relax.d RISC-V: Updated the default ISA spec to 20191213. 2022-01-07 18:48:29 +08:00
code-model-01.ld RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-02.ld RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medany-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medany-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medany-weakref-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medany-weakref-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medlow-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medlow-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medlow-weakref-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-medlow-weakref-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medany-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medany-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medany-weakref-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medany-weakref-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medlow-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medlow-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medlow-weakref-01.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model-relax-medlow-weakref-02.d RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
code-model.s RISC-V: Added ld testcases for the medlow and medany code models. 2021-12-14 13:21:20 +08:00
disas-jalr.d
disas-jalr.s
gp-test-lib.sd
gp-test.s
gp-test.sd
ifunc-nonplt-exe.rd
ifunc-nonplt-pic.rd
ifunc-nonplt-pie.rd
ifunc-nonplt.d
ifunc-nonplt.s
ifunc-plt-01-exe.rd
ifunc-plt-01-pic.rd
ifunc-plt-01-pie.rd
ifunc-plt-01.d
ifunc-plt-01.s
ifunc-plt-02-exe.rd
ifunc-plt-02-pic.rd
ifunc-plt-02-pie.rd
ifunc-plt-02.d
ifunc-plt-02.s
ifunc-plt-got-overwrite-exe.rd
ifunc-plt-got-overwrite-pic.rd
ifunc-plt-got-overwrite-pie.rd
ifunc-plt-got-overwrite.d
ifunc-plt-got-overwrite.s
ifunc-reloc-call-01-exe.rd
ifunc-reloc-call-01-pic.rd
ifunc-reloc-call-01-pie.rd
ifunc-reloc-call-01.d
ifunc-reloc-call-01.s
ifunc-reloc-call-02-exe.rd
ifunc-reloc-call-02-pic.rd
ifunc-reloc-call-02-pie.rd
ifunc-reloc-call-02.d
ifunc-reloc-call-02.s
ifunc-reloc-data-exe.rd
ifunc-reloc-data-pic.rd
ifunc-reloc-data-pie.rd
ifunc-reloc-data.d
ifunc-reloc-data.s
ifunc-reloc-got-exe.rd
ifunc-reloc-got-pic.rd
ifunc-reloc-got-pie.rd
ifunc-reloc-got.d
ifunc-reloc-got.s
ifunc-reloc-pcrel-exe.rd
ifunc-reloc-pcrel-pic.rd
ifunc-reloc-pcrel-pie.rd
ifunc-reloc-pcrel.d
ifunc-reloc-pcrel.s
ifunc-seperate-caller-nonplt.s
ifunc-seperate-caller-pcrel.s
ifunc-seperate-caller-plt.s
ifunc-seperate-nonplt-exe.d
ifunc-seperate-nonplt-pic.d
ifunc-seperate-nonplt-pie.d
ifunc-seperate-pcrel-pic.d
ifunc-seperate-pcrel-pie.d
ifunc-seperate-plt-exe.d
ifunc-seperate-plt-pic.d
ifunc-seperate-plt-pie.d
ifunc-seperate-resolver.s
ld-riscv-elf.exp RISC-V: Stop reporting warnings for mismatched extension versions 2022-02-08 08:23:28 -08:00
lib-nopic-01a.s
lib-nopic-01b.d
lib-nopic-01b.s
pcgp-relax-01.d RISC-V: Added ld testcase for pcgp relaxation. 2021-10-22 16:44:43 +08:00
pcgp-relax-01.s RISC-V: Added ld testcase for pcgp relaxation. 2021-10-22 16:44:43 +08:00
pcgp-relax-02.d RISC-V: Added ld testcase for pcgp relaxation. 2021-10-22 16:44:43 +08:00
pcgp-relax-02.s RISC-V: Added ld testcase for pcgp relaxation. 2021-10-22 16:44:43 +08:00
pcrel-lo-addend-2a.d
pcrel-lo-addend-2a.s
pcrel-lo-addend-2b.d
pcrel-lo-addend-2b.s
pcrel-lo-addend-3.ld RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend-3a.d RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend-3a.s RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend-3b.d RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend-3b.s RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend-3c.d RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend-3c.s RISC-V: Clarify the addends of pc-relative access. 2021-06-22 17:14:55 +08:00
pcrel-lo-addend.d
pcrel-lo-addend.s
relax-twice-1.s elf/riscv: Fix relaxation with aliases [PR28021] 2021-07-06 15:49:03 +02:00
relax-twice-2.s elf/riscv: Fix relaxation with aliases [PR28021] 2021-07-06 15:49:03 +02:00
relax-twice.ver elf/riscv: Fix relaxation with aliases [PR28021] 2021-07-06 15:49:03 +02:00
relro-relax-lui.d
relro-relax-lui.s
relro-relax-pcrel.d
relro-relax-pcrel.s
variant_cc-1.s RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC. 2021-11-19 09:32:19 +08:00
variant_cc-2.s RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC. 2021-11-19 09:32:19 +08:00
variant_cc-now.d RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC. 2021-11-19 09:32:19 +08:00
variant_cc-r.d RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC. 2021-11-19 09:32:19 +08:00
variant_cc-shared.d RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC. 2021-11-19 09:32:19 +08:00
weakref32.d
weakref32.s
weakref64.d
weakref64.s
weakref.ld