..
aarch64
sim: callback: expose argv & environ
2021-11-16 01:13:39 -05:00
arm
sim: install various doc files
2021-11-19 03:36:45 -05:00
avr
sim: split program path out of argv vector
2021-11-15 02:53:29 -05:00
bfin
sim: syscall: hoist argc/argn/argnlen to common code
2021-11-16 02:13:42 -05:00
bpf
sim: callback: expose argv & environ
2021-11-16 01:13:39 -05:00
common
sim: add checks to core headers to prevent incorrect common building
2021-11-28 14:28:35 -05:00
cr16
sim: cr16: switch to new target-newlib-syscall
2021-11-28 13:23:58 -05:00
cris
sim: callback: expose argv & environ
2021-11-16 01:13:39 -05:00
d10v
sim: d10v: switch to new target-newlib-syscall
2021-11-28 13:23:58 -05:00
erc32
sim: install various doc files
2021-11-19 03:36:45 -05:00
example-synacor
sim: callback: expose argv & environ
2021-11-16 01:13:39 -05:00
frv
sim: frv: resolve syscalls dynamically
2021-11-28 01:08:25 -05:00
ft32
sim: callback: expose argv & environ
2021-11-16 01:13:39 -05:00
h8300
Fix intermittent failures on the H8, particularly H8/SX tests.
2021-11-20 13:06:15 -05:00
igen
sim: hoist mn10300 & v850 igen rules up to common builds
2021-11-02 22:59:07 -04:00
iq2000
sim: iq2000/lm32/m32c/moxie/rx: switch to new target-newlib-syscall.h
2021-11-28 13:23:58 -05:00
lm32
sim: iq2000/lm32/m32c/moxie/rx: switch to new target-newlib-syscall.h
2021-11-28 13:23:58 -05:00
m4
sim: testsuite: setup per-port toolchain settings for multitarget build
2021-11-28 21:55:15 -05:00
m32c
sim: iq2000/lm32/m32c/moxie/rx: switch to new target-newlib-syscall.h
2021-11-28 13:23:58 -05:00
m32r
sim: callback: expose argv & environ
2021-11-16 01:13:39 -05:00
m68hc11
sim: split program path out of argv vector
2021-11-15 02:53:29 -05:00
mcore
sim: mcore: switch to new target-newlib-syscall
2021-11-28 13:23:59 -05:00
microblaze
sim: split program path out of argv vector
2021-11-15 02:53:29 -05:00
mips
sim: drop unused gentmap & nltvals.def logic
2021-11-28 13:24:00 -05:00
mn10300
sim: mn10300: resolve syscalls dynamically
2021-11-28 01:01:50 -05:00
moxie
sim: iq2000/lm32/m32c/moxie/rx: switch to new target-newlib-syscall.h
2021-11-28 13:23:58 -05:00
msp430
sim: split program path out of argv vector
2021-11-15 02:53:29 -05:00
or1k
sim: install various doc files
2021-11-19 03:36:45 -05:00
ppc
sim: nltvals: pull target syscalls out into a dedicated source file
2021-11-28 13:23:57 -05:00
pru
sim: callback: expose argv & environ
2021-11-16 01:13:39 -05:00
riscv
sim: riscv: switch to new target-newlib-syscall
2021-11-28 13:23:58 -05:00
rl78
sim: rl78: drop obsolete manual dependency rules
2021-10-31 05:09:09 -04:00
rx
sim: iq2000/lm32/m32c/moxie/rx: switch to new target-newlib-syscall.h
2021-11-28 13:23:58 -05:00
sh
sim: sh: switch to new target-newlib-syscall
2021-11-28 13:23:58 -05:00
testsuite
sim: testsuite: drop most specific istarget checks
2021-11-28 21:55:16 -05:00
v850
sim: v850: switch to new target-newlib-syscall
2021-11-28 13:23:58 -05:00
.gitignore
sim: drop unused gentmap & nltvals.def logic
2021-11-28 13:24:00 -05:00
aclocal.m4
sim: unify reserved instruction bits settings
2021-07-01 20:53:00 -04:00
arch-subdir.mk.in
sim: ppc: fallback when ln is not available [PR sim/18864]
2021-10-03 11:36:30 -04:00
ChangeLog-2021
sim: rename ChangeLog files to ChangeLog-2021
2021-08-17 20:27:36 -04:00
config.h.in
sim: bfin: add support for SDL2
2021-09-13 22:45:19 -04:00
configure
sim: testsuite: setup per-port toolchain settings for multitarget build
2021-11-28 21:55:15 -05:00
configure.ac
sim: testsuite: setup per-port toolchain settings for multitarget build
2021-11-28 21:55:15 -05:00
COPYING
sim: clarify license text via COPYING file
2021-11-06 01:44:06 -04:00
MAINTAINERS
gdb/sim: update my email address
2021-11-02 09:20:24 +00:00
Makefile.am
sim: nltvals: pull target syscalls out into a dedicated source file
2021-11-28 13:23:57 -05:00
Makefile.in
sim: testsuite: support parallel execution
2021-11-28 21:55:15 -05:00
README-HACKING
sim: nltvals: pull target syscalls out into a dedicated source file
2021-11-28 13:23:57 -05:00