Jaydeep Patil 1c37b30945 sim/riscv: fix JALR instruction simulation ... Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written before using it to calculate destination address. This commit also improves testutils.inc for riscv; make use of pushsection and popsection when adding things to .data, and setup the %gp global pointer register within the 'start' macro. Approved-By: Andrew Burgess <aburgess@redhat.com>		2023-10-18 17:55:31 +01:00
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aarch64
arm
avr
bfin
bpf	bpf: sim: do not overflow instruction immediates in tests	2023-07-31 11:09:47 +02:00
common
config
cr16
cris
d10v
example-synacor
frv
ft32
h8300
iq2000
lib	sim prune_warnings	2023-08-19 12:41:32 +09:30
lm32
m32c
m32r
m68hc11
mcore	[RFA] Fix for mcore simulator	2023-10-11 16:31:11 -06:00
microblaze
mips
mn10300
moxie
msp430
or1k	sim: or1k: Eliminate dangerous RWX load segments	2023-08-24 07:03:48 +01:00
pru
riscv	sim/riscv: fix JALR instruction simulation	2023-10-18 17:55:31 +01:00
sh
v850
.gitignore
ChangeLog-2021
local.mk