binutils-gdb/sim
Jaydeep Patil 1c37b30945 sim/riscv: fix JALR instruction simulation
Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written
before using it to calculate destination address.

This commit also improves testutils.inc for riscv; make use of
pushsection and popsection when adding things to .data, and setup the
%gp global pointer register within the 'start' macro.

Approved-By: Andrew Burgess <aburgess@redhat.com>
2023-10-18 17:55:31 +01:00
..
aarch64
arm
avr
bfin
bpf
common
cr16
cris
d10v
erc32
example-synacor
frv
ft32
h8300
igen
iq2000
lm32
m4
m32c
m32r
m68hc11
mcore
microblaze
mips
mn10300
moxie
msp430
or1k
ppc
pru
riscv sim/riscv: fix JALR instruction simulation 2023-10-18 17:55:31 +01:00
rl78
rx
sh
testsuite sim/riscv: fix JALR instruction simulation 2023-10-18 17:55:31 +01:00
v850
.gitignore
aclocal.m4
arch-subdir.mk.in
ChangeLog-2021
config.h.in
configure
configure.ac
COPYING
gdbinit.in
MAINTAINERS
Makefile.am
Makefile.in
README-HACKING
semcrisv32f-switch.c