Mike Frysinger 2b12772f43 sim: bfin: add OTP output port ... This doesn't currently generate any interrupts (as there doesn't appear to be any documentation to *when* it would even do so), but since the HRM does say an interrupt line exists between the OTP and the SIC, add one for completeness sake. This will make a follow up patch easier. Signed-off-by: Mike Frysinger <vapier@gentoo.org>		2011-04-01 22:32:04 +00:00
..
bfroms
aclocal.m4
bfin-sim.c	sim: bfin: fix sign extension with 16bit acc add insns	2011-03-29 01:41:49 +00:00
bfin-sim.h
ChangeLog	sim: bfin: add OTP output port	2011-04-01 22:32:04 +00:00
config.in
configure	sim: bfin: regen configure to include new cfi device	2011-03-29 18:39:51 +00:00
configure.ac
devices.c
devices.h	sim: bfin: fix inverted W1C logic	2011-03-24 03:17:14 +00:00
dv-bfin_cec.c	sim: bfin: fix inverted W1C logic	2011-03-24 03:17:14 +00:00
dv-bfin_cec.h
dv-bfin_ctimer.c
dv-bfin_ctimer.h
dv-bfin_dma.c
dv-bfin_dma.h
dv-bfin_dmac.c
dv-bfin_dmac.h
dv-bfin_ebiu_amc.c
dv-bfin_ebiu_amc.h
dv-bfin_ebiu_ddrc.c
dv-bfin_ebiu_ddrc.h
dv-bfin_ebiu_sdc.c
dv-bfin_ebiu_sdc.h
dv-bfin_emac.c	sim: bfin: fix inverted W1C logic	2011-03-24 03:17:14 +00:00
dv-bfin_emac.h
dv-bfin_eppi.c	sim: bfin: fix inverted W1C logic	2011-03-24 03:17:14 +00:00
dv-bfin_eppi.h
dv-bfin_evt.c
dv-bfin_evt.h
dv-bfin_gpio.c	sim: bfin: add hw tracing to gpio/sic port events	2011-03-25 00:13:57 +00:00
dv-bfin_gpio.h
dv-bfin_gptimer.c
dv-bfin_gptimer.h
dv-bfin_jtag.c	sim: bfin: fix inverted W1C logic	2011-03-24 03:17:14 +00:00
dv-bfin_jtag.h
dv-bfin_mmu.c
dv-bfin_mmu.h
dv-bfin_nfc.c	sim: bfin: fix inverted W1C logic	2011-03-24 03:17:14 +00:00
dv-bfin_nfc.h
dv-bfin_otp.c	sim: bfin: add OTP output port	2011-04-01 22:32:04 +00:00
dv-bfin_otp.h
dv-bfin_pll.c
dv-bfin_pll.h
dv-bfin_ppi.c	sim: bfin: fix inverted W1C logic	2011-03-24 03:17:14 +00:00
dv-bfin_ppi.h
dv-bfin_rtc.c	sim: bfin: fix inverted W1C logic	2011-03-24 03:17:14 +00:00
dv-bfin_rtc.h
dv-bfin_sic.c	sim: bfin: add hw tracing to gpio/sic port events	2011-03-25 00:13:57 +00:00
dv-bfin_sic.h
dv-bfin_spi.c	sim: bfin: fix inverted W1C logic	2011-03-24 03:17:14 +00:00
dv-bfin_spi.h
dv-bfin_trace.c
dv-bfin_trace.h
dv-bfin_twi.c	sim: bfin: fix inverted W1C logic	2011-03-24 03:17:14 +00:00
dv-bfin_twi.h	sim: bfin: fix typo in TWI stat reg	2011-03-24 03:16:22 +00:00
dv-bfin_uart2.c	sim: bfin: fix inverted W1C logic	2011-03-24 03:17:14 +00:00
dv-bfin_uart2.h
dv-bfin_uart.c
dv-bfin_uart.h	sim: bfin: define more UART LSR bits	2011-03-24 03:16:50 +00:00
dv-bfin_wdog.c
dv-bfin_wdog.h
dv-bfin_wp.c
dv-bfin_wp.h
dv-eth_phy.c
gui.c
gui.h
insn_list.def
interp.c
linux-fixed-code.h
linux-fixed-code.s
linux-targ-map.h
machs.c
machs.h
Makefile.in
proc_list.def
sim-main.h
tconfig.in
TODO	sim: bfin: document SIC limitation	2011-03-24 03:18:17 +00:00