binutils-gdb/include/opcode
Xiao Zeng 0b4595be3f RISC-V: Add support for Zvfbfwma extension
This implements the Zvfbfwma extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfwma---vector-bf16-widening-mul-add>

1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension."
  1.1 In Embedded    Processor: Zvfbfwma -> Zvfbfmin -> Zve32f
  1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V
  1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin

2 Depending on different usage scenarios, the Zvfbfwma extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies in
scenario of Embedded Processor. This is consistent with the processing
strategy in Zvfbfmin. In scenario of Application Processor, it is
necessary to explicitly indicate the dependent 'V' extension.

For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=38dd4e26e07c6be7cf4d169141ee4f3a03f3a09d>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfwma.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Updated.
	* testsuite/gas/riscv/march-help.l: Ditto.
	* testsuite/gas/riscv/zvfbfwma.d: New test.
	* testsuite/gas/riscv/zvfbfwma.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VFWMACCBF16_VF): Define.
	(MASK_VFWMACCBF16_VF): Ditto.
	(MATCH_VFWMACCBF16_VV): Ditto.
	(MASK_VFWMACCBF16_VV): Ditto.
	(DECLARE_INSN): New declarations for Zvfbfwma.
	* opcode/riscv.h (enum riscv_insn_class): Add
	INSN_CLASS_ZVFBFWMA

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvfbfwma instructions.
2024-06-06 16:10:53 +08:00
..
aarch64.h gas, aarch64: Add SVE2 lut extension 2024-05-28 17:28:29 +01:00
alpha.h
arc-attrs.h
arc-func.h
arc.h arc: Put DBNZ instruction to a separate class 2024-02-14 11:36:52 +01:00
arm.h arm: remove disassembly support for the FPA co-processor 2024-06-05 17:45:45 +01:00
avr.h
bfin.h
bpf.h bpf: there is no ldinddw nor ldabsdw instructions 2024-01-29 19:22:41 +01:00
cgen.h
ChangeLog-0415
ChangeLog-9103
convex.h
cr16.h
cris.h
crx.h
csky.h
d10v.h
d30v.h
dlx.h
ft32.h
h8300.h
hppa.h
i386.h
ia64.h
kvx.h kvx: gas: rename: or -> ior, xor -> eor 2024-02-20 12:07:57 +01:00
loongarch.h LoongArch: Add -mignore-start-align option 2024-04-20 12:10:40 +08:00
m68hc11.h
m68k.h
metag.h
mips.h
mmix.h
mn10200.h
mn10300.h
moxie.h
msp430-decode.h
msp430.h
nds32.h
nfp.h
nios2.h
nios2r1.h
nios2r2.h
np1.h
ns32k.h
pdp11.h
pj.h
pn.h
ppc.h
pru.h
pyr.h
riscv-opc.h RISC-V: Add support for Zvfbfwma extension 2024-06-06 16:10:53 +08:00
riscv.h RISC-V: Add support for Zvfbfwma extension 2024-06-06 16:10:53 +08:00
rl78.h
rx.h
s12z.h
s390.h s390: Warn when register name type does not match operand 2024-03-01 12:45:14 +01:00
score-datadep.h
score-inst.h
sparc.h
spu-insns.h
spu.h
tic4x.h
tic6x-control-registers.h
tic6x-insn-formats.h
tic6x-opcode-table.h
tic6x.h
tic30.h
tic54x.h
tilegx.h
tilepro.h
v850.h
vax.h
visium.h
wasm.h
xgate.h