Indu Bhagat 29085f7243 gas: aarch64: add experimental support for SCFI ... For synthesizing CFI (SCFI) for hand-written asm, the SCFI machinery in GAS works on the generic GAS insns (ginsns). This patch adds support in the aarch64 backend to create ginsns for a subset of the supported machine instructions. The subset includes the minimal necessary instructions to ensure SCFI correctness: - Any potential register saves and unsaves. Hence, process instructions belonging to a variety of iclasses involving str, ldr, stp, ldp. - Any change of flow instructions. This includes all conditional and unconditional branches, call (bl, blr, etc.) and return. - Most importantly, any instruction that could affect the two registers of interest: REG_SP, REG_FP. This set includes all pre-indexed and post-indexed memory operations, with writeback, on the stack. This set must also include other instructions (e.g., arithmetic insns) where the destination register is one of the afore-mentioned registers. With respect to callee-saved registers in Aarch64, FP/Advanced SIMD registers D8-D15 are included along with the relevant GPRs. Calculating offsets for loads and stores especially for Q registers needs special attention here. As an example, str q8, [sp, #16] On big-endian: STR Qn stores as a 128-bit integer (MSB first), hence, should record D8 as being saved at sp+24 rather than sp+16. On little-endian: should record D8 as being saved at sp+16 D8-D15 are the low 64 bits of Q8-Q15, and of Z8-Z15 if SVE is used; hence, they remain "interesting" for SCFI purposes in such cases. A CFI save slot always represents the low 64 bits, regardless of whether a save occurs on D, Q or Z registers. Currently, the ginsn creation machinery can handle D and Q registers on little-endian and big-endian. Apart from creating ginsn, another key responsibility of the backend is to make sure there are safeguards in place to detect and alert if an instruction of interest may have been skipped. This is done via aarch64_ginsn_unhandled () (similar to the x86 backend). This function , hence, is also intended to alert when future ISA changes may otherwise render SCFI results incorrect, because of missing ginsns for the newly added machine instructions. At this time, becuase of the complexities wrt endianness in handling Z register usage, skip sve_misc opclass altogether for now. The SCFI machinery will error out (using the aarch64_ginsn_unhandled () code path) though if Z register usage affects correctness. The current SCFI machinery does not currently synthesize the PAC-related, aarch64-specific CFI directives: .cfi_b_key_frame. The support for this is planned for near future. SCFI is enabled for ELF targets only. gas/ * config/tc-aarch64-ginsn.c: New file. * config/tc-aarch64.c (md_assemble): Include tc-aarch64-ginsn.c file. Invoke aarch64_ginsn_new. * config/tc-aarch64.h (TARGET_USE_GINSN): Define for SCFI enablement. (TARGET_USE_SCFI): Likewise. (SCFI_MAX_REG_ID): New definition. (REG_FP): Likewise. (REG_LR): Likewise. (REG_SP): Likewise. (SCFI_INIT_CFA_OFFSET): Likewise. (SCFI_CALLEE_SAVED_REG_P): Likewise. (aarch64_scfi_callee_saved_p): New declaration.		2024-07-18 20:54:14 -07:00
..
atof-ieee.c
atof-vax.c
bfin-aux.h
bfin-defs.h
bfin-lex-wrapper.c
bfin-lex.l
bfin-parse.y
e-crisaout.c
e-criself.c
e-i386aout.c
e-i386coff.c
e-i386elf.c
e-mipself.c
itbl-mips.h
kvx-parse.c
kvx-parse.h
loongarch-lex-wrapper.c
loongarch-lex.h
loongarch-lex.l
loongarch-parse.y
m68k-parse.h
m68k-parse.y
obj-aout.c
obj-aout.h
obj-coff-seh.c
obj-coff-seh.h
obj-coff.c
obj-coff.h
obj-ecoff.c
obj-ecoff.h
obj-elf.c
obj-elf.h
obj-evax.c
obj-evax.h
obj-fdpicelf.c
obj-fdpicelf.h
obj-macho.c
obj-macho.h
obj-multi.c
obj-multi.h
obj-som.c
obj-som.h
rl78-defs.h
rl78-parse.y
rx-defs.h
rx-parse.y
tc-aarch64-ginsn.c	gas: aarch64: add experimental support for SCFI	2024-07-18 20:54:14 -07:00
tc-aarch64.c	gas: aarch64: add experimental support for SCFI	2024-07-18 20:54:14 -07:00
tc-aarch64.h	gas: aarch64: add experimental support for SCFI	2024-07-18 20:54:14 -07:00
tc-alpha.c
tc-alpha.h
tc-arc.c
tc-arc.h
tc-arm.c	mve: Fix encoding for vcvt[bt] single-half float conversion instructions	2024-07-04 13:48:26 +01:00
tc-arm.h
tc-avr.c
tc-avr.h
tc-bfin.c
tc-bfin.h
tc-bpf.c
tc-bpf.h
tc-cr16.c
tc-cr16.h
tc-cris.c
tc-cris.h
tc-crx.c
tc-crx.h
tc-csky.c
tc-csky.h
tc-d10v.c
tc-d10v.h
tc-d30v.c
tc-d30v.h
tc-dlx.c
tc-dlx.h
tc-epiphany.c
tc-epiphany.h
tc-fr30.c
tc-fr30.h
tc-frv.c
tc-frv.h
tc-ft32.c
tc-ft32.h
tc-generic.c
tc-generic.h
tc-h8300.c
tc-h8300.h
tc-hppa.c
tc-hppa.h
tc-i386-intel.c
tc-i386.c	x86/APX: remove two inconsistencies	2024-07-12 12:28:03 +02:00
tc-i386.h	gas: Enhance arch-specific SFrame configuration descriptions	2024-07-04 10:34:12 +02:00
tc-ia64.c
tc-ia64.h
tc-ip2k.c
tc-ip2k.h
tc-iq2000.c
tc-iq2000.h
tc-kvx.c
tc-kvx.h
tc-lm32.c
tc-lm32.h
tc-loongarch.c	LoongArch: add .option directive	2024-06-18 10:40:23 +08:00
tc-loongarch.h	LoongArch: Make align symbol be in same section with alignment directive	2024-06-04 19:47:20 +08:00
tc-m32c.c
tc-m32c.h
tc-m32r.c
tc-m32r.h
tc-m68hc11.c
tc-m68hc11.h
tc-m68k.c
tc-m68k.h
tc-m68851.h
tc-mcore.c
tc-mcore.h
tc-mep.c
tc-mep.h
tc-metag.c
tc-metag.h
tc-microblaze.c
tc-microblaze.h
tc-mips.c	Revert "MIPS/GAS: Omit LI 0 for condition trap"	2024-07-13 06:00:43 +01:00
tc-mips.h
tc-mmix.c
tc-mmix.h
tc-mn10200.c
tc-mn10200.h
tc-mn10300.c
tc-mn10300.h
tc-moxie.c
tc-moxie.h
tc-msp430.c
tc-msp430.h
tc-mt.c
tc-mt.h
tc-nds32.c
tc-nds32.h
tc-nios2.c
tc-nios2.h
tc-ns32k.c
tc-ns32k.h
tc-or1k.c
tc-or1k.h
tc-pdp11.c
tc-pdp11.h
tc-pj.c
tc-pj.h
tc-ppc.c
tc-ppc.h
tc-pru.c
tc-pru.h
tc-riscv.c	RISC-V: Fix BFD_RELOC_RISCV_PCREL_LO12_S patch issue	2024-07-04 21:36:48 +08:00
tc-riscv.h
tc-rl78.c
tc-rl78.h
tc-rx.c
tc-rx.h
tc-s12z.c
tc-s12z.h
tc-s390.c
tc-s390.h
tc-score7.c
tc-score.c
tc-score.h
tc-sh.c
tc-sh.h
tc-sparc.c
tc-sparc.h
tc-spu.c
tc-spu.h
tc-tic4x.c
tc-tic4x.h
tc-tic6x.c
tc-tic6x.h
tc-tic30.c
tc-tic30.h
tc-tic54x.c
tc-tic54x.h
tc-tilegx.c
tc-tilegx.h
tc-tilepro.c
tc-tilepro.h
tc-v850.c
tc-v850.h
tc-vax.c
tc-vax.h
tc-visium.c
tc-visium.h
tc-wasm32.c
tc-wasm32.h
tc-xgate.c
tc-xgate.h
tc-xstormy16.c
tc-xstormy16.h
tc-xtensa.c
tc-xtensa.h
tc-z8k.c
tc-z8k.h
tc-z80.c
tc-z80.h
te-386bsd.h
te-aix5.h
te-aix.h
te-armeabi.h	arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFP	2024-06-05 17:45:45 +01:00
te-armfbsdeabi.h
te-armfbsdvfp.h	arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFP	2024-06-05 17:45:45 +01:00
te-armlinuxeabi.h	arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFP	2024-06-05 17:45:45 +01:00
te-cloudabi.h
te-csky_abiv1_linux.h
te-csky_abiv1.h
te-csky_abiv2_linux.h
te-csky_abiv2.h
te-dragonfly.h
te-freebsd.h
te-generic.h
te-gnu.h
te-go32.h
te-haiku.h
te-hppa64.h
te-hppa.h
te-hppalinux64.h
te-hpux.h
te-interix.h
te-irix.h
te-linux.h
te-lynx.h
te-macos.h
te-nacl.h	arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFP	2024-06-05 17:45:45 +01:00
te-nbsd532.h
te-nbsd.h
te-pc532mach.h
te-pe.h
te-pep.h
te-pepaarch64.h
te-solaris.h
te-tmips.h
te-uclinux.h
te-vms.c
te-vms.h
te-vxworks.h
te-wince-pe.h
vax-inst.h
xtensa-istack.h
xtensa-relax.c
xtensa-relax.h