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https://sourceware.org/git/binutils-gdb.git
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42952a9605
The extended instructions implemented in powerpc_macros aren't used by the disassembler. That means instructions like "sldi r3,r3,2" appear in disassembly as "rldicr r3,r3,2,61", which is annoying since many other extended instructions are shown. Note that some of the instructions moved out of the macro table to the opcode table won't appear in disassembly, because they are aliases rather than a subset of the underlying raw instruction. If enabled, rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all occurrences of rotldi, rldicl, rldicr, rldic and rldimi. (Or many occurrences in the case of clrlsldi if n <= b was added to the extract functions.) The patch also fixes a small bug in opcode sanity checking. include/ * opcode/ppc.h (PPC_OPSHIFT_SH6): Define. opcodes/ * ppc-opc.c (insert_erdn, extract_erdn, insert_eldn, extract_eldn), (insert_crdn, extract_crdn, insert_rrdn, extract_rrdn), (insert_sldn, extract_sldn, insert_srdn, extract_srdn), (insert_erdb, extract_erdb, insert_csldn, extract_csldb), (insert_irdb, extract_irdn): New functions. (ELDn, ERDn, ERDn, RRDn, SRDn, ERDb, CSLDn, CSLDb, IRDn, IRDb): Define and add associated powerpc_operands entries. (powerpc_opcodes): Add "rotrdi", "srdi", "extrdi", "clrrdi", "sldi", "extldi", "clrlsldi", "insrdi" and corresponding record (ie. dot suffix) forms. (powerpc_macros): Delete same from here. gas/ * config/tc-ppc.c (insn_validate): Don't modify value passed to operand->insert for PPC_OPERAND_PLUS1 when calculating mask. Handle PPC_OPSHIFT_SH6. * testsuite/gas/ppc/prefix-reloc.d: Update. * testsuite/gas/ppc/simpshft.d: Update. ld/ * testsuite/ld-powerpc/elfv2so.d: Update. * testsuite/ld-powerpc/notoc.d: Update. * testsuite/ld-powerpc/notoc3.d: Update. * testsuite/ld-powerpc/tlsdesc2.d: Update. * testsuite/ld-powerpc/tlsget.d: Update. * testsuite/ld-powerpc/tlsget2.d: Update. * testsuite/ld-powerpc/tlsopt5.d: Update. * testsuite/ld-powerpc/tlsopt6.d: Update.
102 lines
3.2 KiB
Makefile
102 lines
3.2 KiB
Makefile
#source: elfv2.s
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#as: -a64
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#ld: -melf64ppc -shared
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#objdump: -dr
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.*
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Disassembly of section \.text:
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.* <.*\.plt_call\.f4>:
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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\.\.\.
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.* <.*\.plt_call\.f3>:
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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\.\.\.
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.* <.*\.plt_call\.f5>:
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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\.\.\.
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.* <.*\.plt_call\.f1>:
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (e9 82 80 48|48 80 82 e9) ld r12,-32696\(r2\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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\.\.\.
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.* <.*\.plt_call\.f2>:
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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\.\.\.
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.* <f1>:
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.*: (3c 4c 00 02|02 00 4c 3c) addis r2,r12,2
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.*: (38 42 .. ..|.. .. 42 38) addi r2,r2,.*
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.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
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.*: (f8 21 ff e1|e1 ff 21 f8) stdu r1,-32\(r1\)
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.*: (f8 01 00 30|30 00 01 f8) std r0,48\(r1\)
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.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f1>
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.*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\)
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.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f2>
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.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
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.*: (38 62 80 50|50 80 62 38) addi r3,r2,-32688
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.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f3>
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.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
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.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f4>
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.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
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.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f5>
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.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
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.*: (e8 01 00 30|30 00 01 e8) ld r0,48\(r1\)
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.*: (38 21 00 20|20 00 21 38) addi r1,r1,32
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.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
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.*: (4e 80 00 20|20 00 80 4e) blr
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.* <f5>:
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.*: (4e 80 00 20|20 00 80 4e) blr
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.*: (60 00 00 00|00 00 00 60) nop
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.*
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.*
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.* <__glink_PLTresolve>:
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.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
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.*: (42 9f 00 05|05 00 9f 42) bcl .*
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.*: (7d 68 02 a6|a6 02 68 7d) mflr r11
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.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
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.*: (e8 0b ff f0|f0 ff 0b e8) ld r0,-16\(r11\)
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.*: (7d 8b 60 50|50 60 8b 7d) subf r12,r11,r12
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.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
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.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
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.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
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.*: (78 00 f0 82|82 f0 00 78) srdi r0,r0,2
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\)
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.*: (4e 80 04 20|20 04 80 4e) bctr
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.* <f5@plt>:
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.*: (4b ff ff cc|cc ff ff 4b) b .* <__glink_PLTresolve>
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.* <f3@plt>:
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.*: (4b ff ff c8|c8 ff ff 4b) b .* <__glink_PLTresolve>
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.* <f2@plt>:
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.*: (4b ff ff c4|c4 ff ff 4b) b .* <__glink_PLTresolve>
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.* <f4@plt>:
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.*: (4b ff ff c0|c0 ff ff 4b) b .* <__glink_PLTresolve>
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.* <f1@plt>:
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.*: (4b ff ff bc|bc ff ff 4b) b .* <__glink_PLTresolve>
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